What is a memory compiler?

A memory compiler is a generator that builds on-chip memory instances to your specification: the number of words, the word width and the column mux. Silvaco’s compilers produce single- and dual-port SRAM, 1- and 2-port register file and via ROM instances, each fully characterized and DRC/LVS-clean for one foundry process.

What is the difference between SRAM, register file and ROM?

SRAM is general-purpose read-write memory, single or dual port, in low power, general purpose and high performance variants. A register file is a smaller, dense array with one or two ports on a proprietary low-power architecture. ROM holds fixed code or data, programmed in a single via layer, with no leakage in its array.

What deliverables does a compiler generate?

Each compiler generates fully characterized, DRC/LVS-clean instances with Liberty timing and power models, LEF abstracts and GDSII layout, the views an SoC flow needs to place, route and verify the memory. The compiler team can also tune instances to your area, power and performance targets. Ask an IP specialist for the full list of views.

What is BIST and repair support?

Built-in self-test (BIST) lets a chip test its own memories after manufacture, and repair replaces faulty locations with redundant ones. Silvaco’s SRAM and register file compilers offer optional BIST and repair, with ECC bits and word size and address flexibility for redundancy. Ask which compilers include it for your process.

How is a compiler licensed?

Each compiler is built for one foundry process and licensed as production-ready IP through Silvaco’s IP team. Talk to an IP specialist about terms, an evaluation and the instances you need; the compiler team can also tune instances to your targets. Silvaco does not publish licence terms or prices.

Embedded memory compilers: SRAM, register file and ROM

Q: Which foundries and nodes are supported?

Nineteen compilers are in the PRO IP catalog: TSMC at 40, 55, 90, 110 and 130 nm, including eFlash, high-voltage and BCD processes; GlobalFoundries 22FDX, 22FDX+ and 55LPx; and UMC 110 nm eFlash. The selector above lists every one by part number. For another process, ask a Silvaco IP specialist.

Silvaco memory compilers build SRAM, register file and ROM instances to fit your SoC, for design teams who’d rather configure on-chip memory than design around a catalog IP product.

Talk to an IP specialist Download the IP catalog (PDF)

Choose the memory type, then configure it

A catalog instance arrives with its area and leakage already decided, and you pay for those decisions at integration. A compiler works the other way round. You set the words, width, mux and power modes, and it builds the instance to match. That’s why one Silvaco memory compiler covers designs as far apart as an AI accelerator and a wearable.

Single and dual port SRAM

General-purpose read-write memory in low-power, general-purpose and high-performance variants. At 55 nm and below, nap and retention modes cut leakage while the core holds its data. Run periphery and core from one supply or two, and add a write mask if you need it.

Catalog: 12 compilers · 7 single-port, 5 dual-port · TSMC, GlobalFoundries, UMC · 22–130 nm
SRAM Compiler
1 and 2 port register file

Small, fast arrays that sit right next to the logic, on a Silvaco-proprietary architecture built for density and low power. Standby, retention and shutdown modes trade wake-up time against leakage, and byte-mode writes change part of a word without touching the rest.

Catalog: 5 compilers · 3 one-port, 2 two-port · TSMC, GlobalFoundries · 22–110 nm
Register File Compiler
ROM

Code and fixed data, programmed on a single via layer to keep the array dense and the die cost low. The array itself doesn’t leak. Column mux runs from 8 to 128.

Catalog: 2 compilers · TSMC ULP eFlash · 40 and 55 nm
ROM Compiler

Memory compiler selector

Find the compilers for your foundry and node, with the size range and mux options each one generates.

Silvaco memory compilers by part number, with foundry, node, process, memory type, retention, size, mux and supply voltages, as published in the PRO IP catalog
Part number	Foundry	Node (nm)	Process	Memory type	Retention	Size (bits)	Mux	V (periph)	V (array)
61250	GF	22	FDX	1 Port Register File	No	128–40k	8	0.8	–
61251	GF	22	FDX+	Single-Port SRAM	No	256–1,024k	4, 8, 16	0.8	–
61252	TSMC	40	uLP	Dual-Port SRAM	Yes	64–288k	4	0.9	1.1
61253	TSMC	40	ULP eFlash	Dual-Port SRAM	Yes	64–288k	4	0.9	1.1
61254	TSMC	40	LP	Single-Port SRAM	No	256–576k	4	1.1	–
61255	TSMC	40	ULP eFlash	Via ROM	N/A	1k–1,152k	8 to 128	1.1	–
61256	TSMC	55	ULP eFlash	1 Port Register File	Yes	64–32k	2, 4	1.2	–
61257	TSMC	55	HV	2 Port Register File	No	1k–640k	4	1.2	–
61258	TSMC	55	ULP eFlash	2 Port Register File	No	128–64k	4	1.2	–
61259	TSMC	55	LP eFlash	Dual-Port SRAM	No	256–32k	8	1.2	–
61260	TSMC	55	ULP eFlash	Dual-Port SRAM	No	128–64k	4	1.2	–
61261	TSMC	55	HV	Single-Port SRAM	No	512–320k	8, 16	1.2	–
61262	TSMC	55	ULP eFlash	Via ROM	N/A	512–512k	8 to 128	1.2	–
61263	GF	55	LPx	Single-Port SRAM	Yes	320k	4, 8, 16	1.2	–
61264	TSMC	90	LP eFlash	Dual-Port SRAM	Yes	256–80k	8	1.2	–
61265	TSMC	110	HV	1 Port Register File	No	128–20k	4, 8	1.5	–
61266	UMC	110	eFlash	Single-Port SRAM	Yes	256–320k	4, 8, 16	1.5	–
61267	TSMC	130	BCD	Single-Port SRAM	No	128–64k	4, 8, 16	1.5	–
61268	TSMC	130	BCD Plus	Single-Port SRAM	No	128–64k	4, 8, 16	1.5	–

GF = GlobalFoundries. Size runs from the smallest to the largest instance a compiler generates, in bits. Mux is column multiplexing. Retention marks a data-retention mode, and a dash means there’s no separate array supply.

Applications

Where compiled memory goes, on mature nodes and advanced ones alike.

Edge computing and IoT low-power designsLow-leakage sleep modes for battery-powered parts, alongside Low Power Foundation IP
Industrial automation, process control and roboticsMemory on the high-voltage, BCD and eFlash processes industrial parts are built on
Display drivers and DDICsSRAM and register files inside the driver IC
Security and cryptographic processorsSRAM for working data, ROM for fixed code
Audio and voice processing ASICsLow-leakage buffers for always-listening designs

Qualify it from published data

Part numbers, foundries and nodes are all on the record, so your IP qualification can start before the first call.

19 compilerseach with a part number in the PRO IP catalog, 61250 to 61268
TSMC · GlobalFoundries · UMCthe foundries in the current catalog
22–130 nmfrom GlobalFoundries 22FDX to TSMC 130 nm BCD
25+ yearsbuilding compiled memory, with silicon in thousands of designs
Liberty · LEF · GDSIIdelivered with every characterized, DRC/LVS-clean instance

Catalog · PDFSummer 2026

IP product selection guide

Every memory compiler by foundry, node and part number, next to the rest of Silvaco’s licensed IP.
WebinarFebruary 2021

How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers

The architecture behind the three compiler types, and where their density and leakage figures come from.
WebinarJune 2021

Achieving Extreme Low Power IoT Designs with Silvaco’s 55LPx Foundation IP Solution

Low-power foundation IP on GlobalFoundries 55LPx, the same process as compiler 61263.
NewsNovember 2020

Silvaco Acquires Memory Compiler Technology of Dolphin Design SAS

Where the compiler line came from, and the quarter-century of low-power memory work it brought with it.

What can the compiler build on your process?

Send an IP specialist your foundry, node and memory type. You’ll get a technical briefing on configuring the compiler for your application, plus licensing and availability for that process. If the standard options don’t reach your targets, the compiler team can tune an instance to your PPA numbers.

Talk to an IP specialist Download the IP catalog (PDF)

Memory compiler questions

A memory compiler is software that generates on-chip memory instances to a specification: number of words, word width, column mux and power options. You get a layout and a full set of models for exactly that instance. Silvaco’s compilers build single- and dual-port SRAM, 1- and 2-port register files and via-programmed ROM.

SRAM is general-purpose read-write memory with one or two ports. A register file is a smaller array, also with one or two ports, used for fast local storage. ROM holds code or data that never changes, programmed on one via layer. Designing standalone DRAM or NAND instead? See Logic and Memory.

The current catalog lists 19 compilers: TSMC at 40, 55, 90, 110 and 130 nm, including eFlash, high-voltage and BCD processes; GlobalFoundries 22FDX, 22FDX+ and 55LPx; and UMC 110 nm eFlash. If your process isn’t on that list, the compiler team can port to other nodes.

Each instance is foundry-qualified and comes with Liberty timing and power models, LEF abstracts and GDSII layout, all characterized and DRC/LVS-clean. Those are the views your flow reads to place, route and sign off the memory, generated for the exact configuration you chose.

Built-in self-test (BIST) lets a chip test its own memory after manufacture, and repair swaps failing locations for spare ones. Both are optional on the SRAM and register file compilers. ECC bits, plus flexible word size and addressing, give you room to build in redundancy.

You license the compiler rather than a single instance, and each catalog part number covers one foundry process. So you can generate whatever configurations each design needs, from one instance to dozens. Ask an IP specialist about terms for your node.

Embedded memory compilers: SRAM, register file and ROM

Choose the memory type, then configure it

Single and dual port SRAM

1 and 2 port register file

ROM

Memory compiler selector

Applications

Qualify it from published data

IP product selection guide

How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers

Achieving Extreme Low Power IoT Designs with Silvaco’s 55LPx Foundation IP Solution

Silvaco Acquires Memory Compiler Technology of Dolphin Design SAS