Silvaco webinars put the tools to work on real device, circuit and IP problems, presented by Silvaco engineers and by users from Micron, STMicroelectronics and university labs.
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OnlineSPICE ModelingTCAD
TCAD-Aware SPICE Model Extraction with Utmost IV: From Manufacturing to Surrogate Circuit Modeling
Speaker Sean Kelly
Getting a sound model card out of device data usually takes an expert, many optimizer runs and a lot of manual correction. Sean Kelly walks through the new Utmost IV extraction flow, whose reworked optimizer needs far less hand-holding. You follow the data from device measurements to a validated compact SPICE model. From there it goes on into circuit simulation, surrogate modeling and Silvaco FTCO™ workflows.
Missed a session? You can watch 147 Silvaco webinars recorded since 2014, across TCAD, SPICE, custom IC design, design IP and variation analysis. Each one plays from Silvaco's download page after you sign in or register.
Physics-based accuracy and fast design-space exploration usually pull against each other. Dr. Christian Caillat builds interactive FTCO surrogates from multiphysics TCAD data, analytics and machine learning. Structural surrogates follow the geometry as process parameters move; electrical ones reproduce full I-V curves you can query in real time.
Building a test chamber for every geometry or gas chemistry costs too much. Only kinetic simulation captures the non-thermal electron and ion distributions near the sheaths. In VSim, Silvaco's particle-in-cell plasma simulator, John Cary extracts ion energy and angle distributions that feed Victory Process for feature-scale etch.
A photonic device that looks fine as drawn can lose index, confinement and coupling once line-edge roughness, sloped sidewalls and CD shifts arrive from the fab. John Sembower simulates it as manufactured. Fab parameters go into Victory Process and GPU-accelerated FDTD runs in Victory Device; FTCO adds DoE and analytics, starting from the GDS and ending in a digital twin.
At 2 nm and below, nanosheet FETs stop obeying effective-mass shortcuts: quantum effects count and the band structure depends on the device. Dr. Philippe Blaise runs full-device NEGF simulation in Victory Atomistic, up to 10⁵–10⁶× faster than conventional NEGF solvers. Then he sweeps Vth, DIBL, SS and injection velocity through an FTCO workflow.
Wide bandgap devices now go into electric vehicles, renewables and megawatt-scale AI data centers. Britt Brooks applies FTCO to SiC DMOS, vertical GaN and p-GaN HEMTs, pairing large parallel simulation runs with smart DOE and ML surrogates. Calibration, variability and yield prediction all happen before the physical DOE.
A working FinFET flow, with a GAA nanosheet example to show it carries over. Strain, mobility, quantum confinement and band-structure corrections are all calibrated against reference data in Victory TCAD. Jay Zhou then uses Victory Analytics and FTCO™ to explore process and design windows across several parameters at once.
Sensitivity, noise, color and pixel size all compete in a CMOS image sensor. Hamid Soleimani builds TCAD digital twins in Victory TCAD, with Victory DoE and Victory Analytics on top. They expose hidden variables and process, device and optical trade-offs before a prototype run.
Where GaN earns its place in power and RF, and the Victory TCAD flow for it. Udita Mittal simulates vertical GaN and p-GaN gate structures and explores the design in Victory DoE and Victory Analytics. Then she hands the result to circuit design through Utmost IV SPICE models.
Gate-all-around transistors push device modeling down to the atom. Dr. Philippe Blaise sets up GAA FETs in Victory Atomistic, capturing quantum confinement, crystal orientation, strain and band-structure effects. You get usable I-V curves without needing NEGF theory.
FinFET, RF SOI, LDMOS, DRAM or NAND. Mao Li runs etch, deposition, implant and diffusion in Victory Process, characterizes the result in Victory Device. Then he refines the design using Victory Analytics and Victory DoE.
Smaller geometries multiply parasitic elements, and chasing them through simulation can push out tape-out. Carlos Augusto Berlitz uses Viso on a high-speed LVDS block to find the root cause of parasitic-induced problems with fewer simulation runs.
Shallow junctions let transient diffusion decide the final device, so simple diffusion models fall short. Dr Thomas Grenouilloux takes you through the physics of the Victory Process CMOS diffusion model, out-of-equilibrium defects and dopant co-interactions included. Then he puts it to work in your decks on a planar CMOS example.
Calibrating TCAD by hand is slow trial and error. Dr. Stefania Carapezzi runs the experiment set in Victory DoE. Victory Analytics then fits TCAD parameters to measured data with machine learning, on an AlGaN/GaN HEMT.
Can a channel a few atomic layers thick replace silicon? Only atomistic simulation can say. Dr. Philippe Blaise prototypes 2D-TMD transistors, a TFET among them, in Victory Atomistic inside an ordinary TCAD environment.
Micron's DRAM and 3D NAND work needs models of hard-to-build structures and of how process variation shifts electrical results. Sumeet Pandey of Micron Technology demonstrates stress modeling, sensitivity analysis and virtual process models on Silvaco's FTCO™ platform. You also see how the two companies built a digital twin of a fab process.
Process DOEs on real wafers mean weeks or months of expensive iterations. Dr. Christian Caillat shows an FTCO flow, already in production use, that runs the same DOE on a physics-based digital twin trained with machine learning. The examples: optimizing an STI trench, and RTSM, which models 2D structures in real time.
Short-circuit and UIS tests push SiC devices past normal limits. Salvatore Cascino of STMicroelectronics simulates a surface defect dot in the active area with mixed-mode TCAD. He moves it between the flat body/drain interface, the SiC/oxide channel interface and the curved body/drain interface, and shows how position changes short-circuit behavior.
Lateral GaN switches near 650 V still sit short of the material's RDS(on)×A limit. Dr. Eldad Bahat-Treidel of the Ferdinand-Braun-Institut uses Silvaco tools on two answers. One is the vertical GaN fin-MISFET, with its drift region and edge termination; the other is the lateral HFET on an AlN buffer, including the trapping behind dynamic on-resistance.
Si, GaN and SiC power devices each need their own modeling approach. Bogdan Tudor weighs compact models against macromodels and handles the bias-dependent capacitances of power FETs. Tuning to dynamic data, parasitics and accuracy follow, with TCAD-based extraction examples.
Matching the etch profile on a TEM image is a routine TCAD chore. Alexander Toifl uses Victory Process geometric etch models for fin shaping, bowing and twisting, and self-aligned multi-patterning. 3D NAND trenches and contact holes get the ETCH POLYLINE and ETCH DRY commands.
Most TFTs in production are 4-terminal devices, and SmartSpice has a 4-terminal TFT compact model for them. Jody Matos explains what that model frees up for modeling and design teams, then simulates image retention with SmartSpice Flex Modeling.
Car vision, industrial machines and high-speed links all turn light into signal through photodiodes. Sungwon Kong applies TCAD across detector types and materials, then simulates an InGaAs avalanche photodiode to pull out its figures of merit.
A foundry that keeps refining its process has to rebuild and revalidate libraries constantly. Faris Amsyar Bin Ahmad Zhaki of SilTerra shows Cello, Viola and SmartSpice cutting the time a small team spends developing and validating standard cell and I/O libraries.
What changed in the Utmost IV 2022 Baseline. The Corner and Retargeting Module was new that year, alongside bias trends, hierarchical macromodels and modeling for GaN HEMTs, displays and nanosheets. TCAD flow integration and Silvaco's SPICE modeling services round it off.
Victory Visual post-processes results from every Silvaco TCAD simulator, on its own or inside DeckBuild. If you know TonyPlot, parts will feel familiar. Thomas Kurzanski goes through sorting data, 2D and 3D views, cut planes, probes, file comparison and atomistic display.
At 5 nm and below, FET design needs atomic-scale simulation. Dr. Philippe Blaise models a narrow silicon nanowire FET in Victory Atomistic: NEGF with electron-phonon scattering and low-rank optimization. You get an I(V) curve in a day without being an NEGF specialist.
An earlier edition of the etch-matching session. Alexander Toifl reproduces fabricated profiles in FinFET and memory structures with Victory Process geometric models. Fin shapes, bowing and twisting, multi-patterning, and 3D NAND trench and contact-hole etch are all covered.
Flat panel and detector designers often stitch together point tools from several vendors. Stefano Pettazzi runs one Silvaco TCAD-to-EDA flow instead: schematic and layout, field-solver parasitic extraction for TFTs, RC back-annotation, and SPICE simulation of large pixel arrays.
Image retention comes from dynamic device effects, hysteresis above all, that ordinary SPICE models leave out. Dr. Jody Matos models them with SmartSpice Flex Modeling so display teams can reproduce the problem at SPICE level and design it out.
Silvaco and Semiconductor Energy Laboratory built a SPICE model for CAAC-IGZO multi-gate FETs, and this update widens the fin geometries it handles. You hear from Makoto Watanabe why the device matters, where the previous model fell short and what changed. In Japanese, with English subtitles.
Silvaco's AMBA AHB subsystems supply the interconnect and functional blocks around the processors in IoT, medical and industrial-controller SoCs. Jim Avant helps you choose between Channel and Fabric architecture, then works through customization, low power, hardware and software security, secure boot and hardware-software co-verification.
A rebroadcast of VLSI-TSA 2022 Special Session T9-2. Dr. Tillmann Kubis presents incoherent scattering models that match measured band-gap narrowing and Urbach tails in III-V semiconductors and TMDs with no fitting parameters. Nanowire transport runs on under one-hundredth of the original compute. He also introduces ROBIN, a method that avoids periodic-boundary artifacts.
Forcing a 4-terminal TFT into a 3-terminal model burdens the modeling team and limits the designers. Dr. Jody Matos introduces the SmartSpice 4-terminal TFT compact model, already in use for metal-oxide, organic, polysilicon and amorphous silicon TFTs, and for LTPS, LTPO and flexible displays.
Proving a 3D power device concept in silicon is expensive for a start-up. Dr. Munaf Rahimo of mqSemi AG used Silvaco 3D TCAD to prove the company's S-MOS cell in 1200 V silicon IGBTs and SiC MOSFETs. He walks through the models and the results.
Extracting and validating SPICE parametric models in Utmost IV, its role in TCAD-based DTCO flows, Device Exploration, and the then-new Corner and Retargeting Module. Bogdan Tudor closes with Silvaco's modeling services.
Substrate parasitics shape RF circuits, and they're hardest to model under large-signal drive. Professor Jean-Pierre Raskin of UCLouvain models small- and large-signal substrate behavior in Victory Device. His large-signal scheme converges and matches measurements from more than 20 silicon-based substrates.
SmartDRC/LVS runs design rule checks, connectivity extraction and layout-versus-schematic for mixed-signal, analog and digital designs. It runs on a multi-CPU architecture with silicon-proven, foundry-certified runsets. Alex Grudanov shows debug in SmartRDE, the PWRL rule language and One-Shot™ layout scanning, all tied to Expert and Gateway.
FinFET design rules often span a whole standard cell and several polygons, so violations stop being local fixes. Osvaldo Martinello picks out the hardest parts of FinFET standard-cell layout and how Cello deals with each.
Process output needs a new mesh before device simulation. Dr. Carlos Bedregal shows Victory Mesh taking a Victory Process structure to Victory Device. He compares Conformal (semi-structured, Cartesian-based) and Delaunay (unstructured) meshing and the refinement options for each.
GaN serves RF and power alike, yet parts of its behavior are still open research. Professor Michael Uren of the University of Bristol uses published examples to show device simulation explaining three effects. They are dynamic on-resistance in GaN-on-Si switches, persistent photoconductivity, and dispersion of transconductance in HEMTs doped with iron.
SPI started at Motorola in 1979. Dual and Quad versions followed, then Octal and Octal DDR, which finally made it fast enough for RAM as well as Flash. Errett Hogrefe introduces Silvaco's Octal SPI Memory Controller: architecture, operating modes, Execute In Place, PSRAM support and a typical integration.
Ten changes in the SmartSpice 2021 Baseline Release. Runs got up to 4x faster with 9x lower memory use, and RHEL/CentOS 8 support arrived with a new GUI. Also in the release: reworked RF phase-noise and periodic steady-state flows, better Spectre® compatibility and External Sampling for Monte Carlo.
Victory Atomistic grew out of NEMO5 from Purdue University and predicts quantum transport at atomic resolution. Dr. Philippe Blaise sets up a nanowire FET and shows the speed-up that makes daily atomistic runs practical, with short tutorial videos.
IBC silicon cells approach their limit of roughly 29%, and perovskite cells already near 26%. James Connolly of GeePs at CentraleSupélec simulates both in TCAD and combines them in a three-terminal tandem model. Then he compares two- and three-terminal designs that go past the single-junction limit.
Rule-based extraction simplifies the structure before it calculates, and the error turns into design margin. Derek Kimpton builds realistic 3D back-end structures in Victory Process for Hipex-FS field-solver extraction, with rule-based and field-solver RCx in one interface.
Battery-powered IoT parts may need three to five years on one battery. Ashish Shrotriya and Guilherme Schlinker cover Silvaco's silicon-proven Foundation IP: memory compilers and standard cell libraries. They explain the techniques built in for low power.
IO and ESD sit on every chip and get harder to design at each new node. Ahmad S. Mazumder lays out the main challenges in advanced-node SoCs and how a complete IO and ESD library can be developed in five weeks.
Patterning the sapphire substrate lifts light extraction in GaN LEDs, and anisotropic wet etching gives the most useful shapes. Alexander Toifl links Victory Process 3D wet-etch simulation to ray tracing in Victory Device, so you can see how each process parameter moves LED efficiency.
Start with the driving TFT, then the pixel, then the full array. This session checks TFT driving characteristics, pixel operation and timing, array timing during scene changes, and the constraints on active devices.
Part one covers CAAC-IGZO FETs from Semiconductor Energy Laboratory and their use in AI applications. Part two covers the CAAC-IGZO FinFET SPICE model that SEL and Silvaco developed together. In Japanese, with English subtitles.
Choosing simulation models, changing material and model properties, and calibrating them for different processes. Dr. Vito Simonka works in the Silvaco Material Database, the METHOD, MATERIAL and INTERFACE statements, and the Silver interface.
RC parasitics grow fast at advanced nodes, and an odd post-layout result can cost days of debugging. Simon-Alexis Abric shows Silvaco's parasitic analysis and debug tools catching problems when an extraction flow changes. They also make the post-layout design easier to read and optimize.
Write your own diffusion model for Victory Process. You start from the annealing model library and a local copy of the model files, write a simple model, then compile it and run it.
Every etch, deposition and thermal step changes stress, so the history matters. Dr. Jin Cho and Dr. Artem Babayan show stress simulation built into the Victory Process flow. Their cases: FinFET bending during STI fill, layer bending during etch, back-end metal line bending and wire-bond stress.
A tour of Silvaco's SPICE modeling software, TechModeler and Utmost IV, and of its modeling services, with recent display, RF and advanced-process examples. Dr. Bogdan Tudor then introduces the Utmost IV Quick-Start Optimization Templates.
What's in SmartSpice 4.44.3.R, and what's planned for the next yearly release. SmartSpice keeps getting faster, uses less memory and adds analog modeling and analysis features.
Silvaco's SRAMs, register files and ROMs have been in ultra-low power, high-density production for 25 years, at more than 12 foundries and IDMs. Eitan Zmora explains the memory technology and architecture, and how it fits with Silvaco standard cells and IOs.
A guided remesh. You take a Victory Process structure into Victory Mesh, choose Conformal or Delaunay, and refine at interfaces, junctions, impurities and regions before handing it to Victory Device. Thomas Jokinen adds structure editing and solid modeling.
Rafael Microelectronics built a wireless IoT SoC around its own Bluetooth, Zigbee and Sub-GHz RF IP and Silvaco's AMBA subsystem. Ken Li of Rafael explains the requirements and the integration, power and memory management included.
Dr. Yuhao Zhang of Virginia Tech's Center for Power Electronics Systems walks through how design teams use 3D Silvaco TCAD on wide and ultra-wide bandgap power devices. The work runs from GaN FinFET and tri-gate design and process simulation to electrothermal and mixed-mode runs, reliability and ruggedness, and vertical GaN trench formation.
Two STMicroelectronics engineers share how they used Cello across several technologies to build standard cell layouts: creation from schematic, optimization, migration and validation. Across the study, development effort fell by about 40% from start to finish.
What the 2020 release of the Silvaco analog custom design flow changes for interoperability, performance and productivity. Fred Sendig goes tool by tool: Gateway schematic capture, SmartView waveforms, Expert layout and Guardian DRC, plus iPDK and OpenAccess support then in development.
SmartSpice HPP partitions transient analog simulation across multicore hardware. Dr. Jody Matos shows where it scales up to 8x better than regular SmartSpice and runs up to 40x faster at acceptable accuracy, pre- or post-layout.
Speakers Kwanyeob Chae, Sean Lee, Ashish Shrotriya
Samsung Foundry's DDR PHY IP, OpenEdges' multi-protocol controller and Silvaco subsystem IP, put together as a plug-and-play DDR memory subsystem. Engineers from all three companies show it for HPC, 5G, automotive and IoT SoCs.
Rule-based full-chip extraction in Hipex is only as accurate as its rule files. Yusuke Ito shows new pattern-matching models that tighten them, then checks the result with the Clever 3D field solver and the Belledonne netlist comparison tool. In Japanese.
Fast interfaces now shape the chips behind AI/ML, smart-city systems and self-driving cars. Ahmad S. Mazumder sets out the main design challenges, good practice for SoCs, and Silvaco's production-proven memory and interconnect IP.
Leti-NSP models multi-gate MOSFETs, stacked nanosheets and FinFETs among them. Dr. Bogdan Tudor walks the parameter extraction flow for vertically stacked nanosheets step by step in Utmost IV, comparing the Verilog-A version with the model built into SmartSpice.
How to secure a hardware and software design built on AMBA, and the Secure AHB Subsystem Silvaco offers for the Arm Cortex-M3. It pairs a secure interconnect fabric with parameterized SRAM and ROM MPUs.
Machine learning has been inside EDA for 20 years, adapted to tight compute, short schedules, noisy data and growing variation at advanced nodes. Dr. Firas Mohamed reviews how those methods are applied, with examples from Silvaco's ML-based tools.
How SmartSpice uses models, and when a built-in model beats custom Verilog-A. Then good practice for writing your own and debugging it from simulation results, with examples and templates online.
Flash is nearing its scaling limits, and OXRAM and CBRAM are candidates to follow it. Dr. Wolfgang Goes uses a ReRAM model built on the Chemistry Module in Victory Device. It shows the chemistry behind resistive switching and the factors that control it.
Samsung Foundry's process capabilities and the IP enablement Silvaco provides on them. It spans HPC, data center, AI/ML, networking and autonomous driving, plus interface, sensor and security IP for 5G and IoT.
Modeling for flat panel displays in Utmost IV. Dr. Bogdan Tudor handles TFTs and their frequency dispersion, OLEDs through Verilog-A models and macromodels, and devices with no compact model yet, all on TCAD-generated data.
FDTD simulates light in arbitrary structures and materials, which is why lighting, display, sensor and photonics designers use it. Dr. Slim Chourou sets up FDTD runs for solar cells, waveguides and LEDs and couples the optics to electrical simulation. He also compares the other methods in Silvaco's Optics Library.
An automated flow from molecular simulation to TCAD for organic LEDs. Density of states and mobility, computed from first principles, feed the device models, so you explore materials and device design in one flow. Presented by Silvaco and Nanomatch, using the SimStack platform.
Quick-Start Optimization Templates in Utmost IV build an optimization project for a given model from your own data, with little prior SPICE modeling experience. Dr. Bogdan Tudor reviews the templates for diode, IGBT, HEMT, TFT, bipolar and MOSFET models, BSIM4 and PSP among them.
I3C V1.1 arrived in January 2020 and runs up to 100 MHz, with fewer pins and lower power than I2C. Paul Kimelman of NXP explains signaling and protocol, dynamic addressing, HDR modes, CCCs, in-band interrupts and integrating I3C cores.
Victory Atomistic, built on Purdue's NEMO5, models electronic and phonon bands and quantum transport in semiconductor and metal nanodevices. You get device structures, solvers, NEGF and scattering from Dr. Philippe Blaise, with nanowire FET, tunnel FET and optoelectronic examples.
Huge extracted RLCK networks slow post-layout simulation to a crawl. Simon-Alexis Abric shows Jivaro reducing them for SPICE and FastSpice users while holding accuracy, and the advanced controls that buy more speed.
V2X connectivity and ADAS hand vehicle control to software, and the attack surface grows with them. Conor Culhane's answer includes isolating critical networks, secure updates, side-channel defenses and key management, plus Silvaco SIPware security IP from TRNG and PUF to secure AES.
The select gate in a 3D NAND cell must leak little during disturb yet drive enough current for read and erase. Dr. Jin Cho uses TCAD to tune its work function, its overlap with source and drain, and trap density. Then he shortens the gate using dummy cells for threshold control.
Drift-diffusion struggles between 4 K and 100 K, numerically and in its physical models, just as cryo-CMOS matters for space, exascale and quantum computing. Dr. Stephen Wilson explains how Silvaco device simulators get past both, on a MOSFET and a silicon avalanche photodiode.
An introduction to Silvaco TCAD for wide bandgap materials. You learn what TCAD is and how it models their processing and electrical behavior, with a GaN FET and a SiC JBS diode as examples.
Each new answer to on-chip variation trades run time against pessimism. Bernardo Culau traces the industry's approaches to sign-off timing, the ones accepted today and what comes next, and where Silvaco fits.
Stellar, now a field-solver mode inside Hipex, handles very large layouts with less memory and runtime, with Clever as the accuracy reference. Sungwon Kong sets up Stellar from the Expert GUI and extracts capacitance for a touch panel.
LCoS spatial light modulators sit in VR and AR headsets, but low-latency, high-resolution AR still needs better pixels. Dr. Debin Li analyzes a phase-only LCoS-SLM in Clever LCD, including what happens as you drive the pixels and shrink them.
Silvaco's automotive communication IP, developed with partners including NXP, Infineon and TI, is production-proven in millions of vehicles. Rajeev Huralikoppi reviews automotive segments, trends and standards, and the controller IP in the SIPware catalog.
Verilog-A put model coding in circuit designers' hands, and with it the job of keeping models stable enough to converge. Dr. Slobodan Mijalkovic gives practical guidance on coding SPICE compact models that hold up in simulation.
Board, IC and package flows all lean on circuit simulation. Graham Bell looks at the flows built on the SmartSpice engine, what helps and hurts them, and how to get the most throughput.
All three parts of the introduction to Silvaco TCAD in one recording. Process and device simulation show what experiments can't, and that feeds performance, yield and time to market.
Expert handles hierarchical layout for analog, mixed-signal, RF, optoelectronic and flat panel designs. Andrei Karabelnikau shows how JavaScript speeds up custom layout editing in it.
A single command file plus a GDSII layout can drive a whole DTCO experiment. Dr. Derek Kimpton builds 3D active devices and BEOL structures on a FinFET example. He extracts SPICE parameters, runs 3D field-solver RC extraction and finishes with circuit simulation.
To get throughput from SPICE, you need to know what happens inside it. Robert Villanueva opens up the SmartSpice core, parallel and FastSPICE analysis modes included.
Flash, newer non-volatile memories and complex SoCs like the Nvidia Xavier and the Apple A12 reuse IP at the architecture level. They still need new IP analyzed down to nanometer and atomic scale. Dr. Babak Taheri argues for simulation, emulation, DTCO and verified IP in that work.
NEMO5, built at Purdue University by more than 65 authors and moving into the Silvaco TCAD suite, predicts bandstructure and transport down to subatomic resolution. Prof. Dr. Tillmann Kubis explains its DFT and molecular-dynamics inputs and real-world effects such as temperature, rough interfaces and doping disorder.
Part 2 picks up the GaN HEMT extraction method with I-V and capacitance data generated in TCAD. Dr. Bogdan Tudor compares symmetric and asymmetric structures and extracts the SPICE I-V and capacitance parameters step by step, with the focus on asymmetric devices.
Advanced nodes multiply the simulations, PVT corners and variation formats that characterization needs. Bernardo Culau explains how to keep results accurate with fast turnaround, then goes through Silvaco's characterization service options and tool flow.
Scaling brings degradation with it, and NBTI is one of the effects industry watches most closely. Dr. Wolfgang Goes uses TCAD to understand, predict and reduce reliability and aging effects in MOS devices.
Less internal RAM and fewer pins cut IoT power, but instruction fetch speed depends on the memory architecture. Errett Hogrefe compares NVM and RAM options for IoT systems, from 4-wire SPI flash to Dual, Quad and Octal variants, with the performance differences measured.
At nanometer lengths, band edges and effective masses become design choices, and carriers stop behaving classically. Gerhard Klimeck uses NEMO's NEGF and atomistic tight-binding approach, validated against experiments over 25 years. He shows how bandstructure changes at that scale and what it does to devices.
AI and ML SoCs need specialized processing, high-bandwidth low-energy memory and reliable fast connectivity. Ahmad S. Mazumder tailors memory and interconnect IP to those efficiency targets.
Bendable displays, smart labels and wearables bring mechanical strain into circuit simulation. Dr. Slobodan Mijalkovic extends SPICE models for TFTs and MOSFETs so strain is accounted for in flexible circuit design and physical verification.
I3C from the MIPI Alliance unifies and extends I2C and SPI for mobile, automotive and IoT. Rajeev Huralikoppi explains what's new in it, and how Silvaco's I3C products let you use its higher speed and lower power.
Variation at new nodes makes brute-force 6-sigma memory verification impractical, and 7-sigma is now a real requirement. Dr. Jean Baptiste Duluc applies VarMan's Variability eXplorer, high-sigma yield and performance-limit analysis and eXtreme Memory Analysis to cut simulation counts while keeping accuracy.
Part 1 of a GaN HEMT model extraction method. Dr. Bogdan Tudor reviews current compact models, in Verilog-A and built-in form, and generates input data in TCAD with and without self-heating. The extraction flow covers symmetric and asymmetric devices and how to set up optimization.
Migrating Foundation IP between compatible nodes saves engineering time and gives a starting layout to optimize in the new technology. Guilherme Schlinker lays out a method for moving standard cell libraries to a new node, then optimizing them.
2D and 3D TCAD is used across CMOS, power and RF devices, optoelectronics, photonics, sensors, displays and MEMS. Dr. Hugh Barnaby of Arizona State University and Dr. Garrett Schlenvogt put device theory into practice with it.
Large companies run hundreds of IP transactions a year with dozens of suppliers, and much of the data involved isn't design data. Warren Savage on managing that metadata at enterprise scale.
Oxide semiconductor TFTs offer high mobility, a wide band gap and a low process temperature, for displays, sensors, solar cells and memory. Dr. Katsumi Abe simulates OS TFTs in Silvaco tools, with mobility and subgap density-of-states models and self-heating.
Bending and stretching shift TFT performance on flexible substrates. Sungwon Kong and Dr. Heetaek Lim compare numerical stress methods with an analytical model. Then they present a non-linear finite element flow for large deformation, stress and strain.
Speakers Ron Werner, Jim Bruister, Shawn Prestridge
Silvaco and IAR Systems pair software tools with Silvaco's AMBA subsystems, the base platform for IoT edge, medical, industrial and wireless gateway SoCs.
When rule-based extraction runs out of accuracy, or the LPE decks don't exist, field solvers on realistic 3D geometry give the answer. Dr. Garrett Schlenvogt extracts RC parasitics from TCAD structures with physics-based solvers.
Finding 3-sigma corners or verifying at 6-sigma for standard cell libraries takes too many simulations. Dr. Prashant Singh shows the VarMan tools, Fast Monte Carlo and high-sigma analysis among them, reducing that count without giving up accuracy.
Silvaco's serial flash interface IP, SPI, QSPI and OSPI, for SoCs that boot from low-power serial flash. Jim Bruister demonstrates Execute in Place with flash from several vendors, and an SPI-to-AHBLite bridge you can use to program external flash.
Wearable and foldable displays need backplane TFTs that survive bending and stretching. Threshold voltage shift under electrical, thermal and mechanical stress is the core problem. Sungwon Kong reviews flexible-display device design and the factors that set device characteristics.
Ion transport and electrochemistry matter both by design, in non-volatile memory and solid-state batteries, and by accident, in degradation. Dr. Carl Hylin introduces the electrochemistry simulation added to Victory Device.
Phones carry many sensors that have to report fast at low power. Paul Kimelman and Warren Savage introduce I3C, the MIPI Alliance standard built for connecting them.
Speakers Steve Broadbent, Matthias Roschke, Sungwon Kong
TCAD techniques for display designers. Electrical and optical simulation of LED and OLED diodes comes first, then LCD transmission across wavelengths and voltages. Last is a-IGZO TFT degradation, the main issue for large, high-definition pixels.
Find power integrity problems before physical design is done. Kim Nguyen has layout engineers estimating EM, IR and thermal conditions early with InVar Prime.
Two extraction tools can give different parasitics for the same design. Jean-Pierre Goujon compares them qualitatively and quantitatively and traces where the differences come from. After that, tool changes, node calibration and PDK updates stop holding CAD teams up.
Radiant simulates LED and OLED devices in one environment. Steve Broadbent focuses on OLEDs, with electrical and optical simulation of multilayer stacks for white OLED development.
SUPREM-IV-based 2D simulators have served for nearly 30 years. Dr. Misha Temkin presents Victory Process as the next step: 1D, 2D and 3D process simulation that takes new materials and processes into a flow.
Plain Monte Carlo no longer meets analog designers' needs at advanced nodes. Dr. David Cartalade's alternative is a VarMan-based flow for statistical analysis of analog circuits.
InVar Prime brings the InVar power integrity tools into layout planning, estimating IR drop, current density and supply network quality early. Alex Samoylov demonstrates the analysis, its inputs and the flow.
DeckBuild and Virtual Wafer Fab are the front ends for running TCAD. Dr. Thomas Binder sets up runs from examples, edits decks, views 2D and 3D structures, and runs DOE and optimization on one workstation or a cluster.
Wide bandgap power simulation has moved from convergence problems to calibration against manufacturing data. Dr. Marek Turowski takes SiC, GaN and Ga₂O₃ devices in turn. He adds electro-thermal single-event simulation and stress in SiC, and validated process simulation for wide bandgap materials.
The Japanese edition: simulation and calibration of SiC, GaN and Ga₂O₃ power devices, stress simulation, and process simulation capabilities then in development for wide bandgap materials. In Japanese.
Speakers Dr. Gediminas Paulavicius, Andrei Karabelnikau, Alex Samoylov
Display circuits have outgrown traditional SPICE. Three Silvaco engineers simulate a TFT panel in SmartSpice Pro, an event-driven multi-rate simulator. Then they speed up FPD layout in Expert and check voltage drop early with InVar Prime.
High aspect ratio trench etching is a key challenge in vertical non-volatile memory. Dr. Andreas Hössinger opens up the models in Victory Process, its open modeling system for trading accuracy against run time, and the ion-enhanced chemical etch model.
Many devices are inherently three-dimensional, and larger structures with cells and terminations need simulating too. Dr. Eric Guichard uses a unified 3D TCAD platform on a vertical LOCOS transistor and on current filaments in a multi-cell IGBT.
FinFET, FDSOI and lower Vdd/Vth push designers into massive Monte Carlo runs that cost time and licenses. Pierre Faubet offers more efficient techniques for variation-aware design.
The TCAD-to-SPICE flow for solar cells and panels. It builds 3D cell structures, gets quantum efficiency and other metrics, and handles light propagation and carrier generation. SPICE extraction for panel design closes it.
InVar models power, voltage and temperature together for reliability analysis. Alex Samoylov covers EM, IR, power and thermal analysis at gate and transistor level, from early checks through signoff, with a short demo.
Heterogeneous 3D integration brings new design problems. Stefano Pettazzi introduces two prototype tools: automatic 3D space partitioning for 3D ICs, and 3D design rule checking.
Extracting HiSIM_HV 2 parameters for high voltage devices. Yoshihisa Iino explains the parameter effects, extracts them in Utmost IV one step at a time and introduces the depletion mode added in HiSIM_HV 2.2.0. In Japanese.
Four common radiation environments, in space and near high-energy sources, change devices through oxide charging and physical damage. Dr. Derek Kimpton simulates total dose, prompt dose, damaging fluence and SEU in TCAD, at high and low dose rates.
SiC is harder to simulate than silicon. Dr. Eric Guichard sets out what accurate SiC power simulation needs, and presents an automated TCAD-to-SPICE flow for developing a silicon IGBT.
A calibration procedure for amorphous silicon TFTs against measured data, focused on leakage current, with density of states and band-to-band tunneling models.
Smaller features make single event effects harder to model and more important to get right. Dr. Christopher Nicklaw models SEE at device and circuit level, along with soft error rates, multi-bit upsets and chip packaging.
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