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MIPI I3C interface IP: controller and target cores

Configurable I3C interface IP for SoC teams moving their sensors onto one two-wire bus: five controller and target cores from Silvaco, delivered as synthesizable soft IP.

Talk to an IP specialist Download the I3C product brief (PDF)

Five I3C IP cores, sized to the role your chip plays

Every core complies with MIPI I3C V1.1.1 and I3C Basic V1.1.1 and supports in-band interrupts. Each one is configurable, so the logic you carry matches the features you use.

  • I3C Advanced Controller

    The MIPI I3C controller for running the bus from your microcontroller subsystem. It hands out dynamic addresses, supports all common command codes and can also serve as a secondary controller. SDR, HDR-DDR and HDR-BT at up to 100 Mbps over 1, 2 or 4 SDA lanes, on an APB 3.0 interface. Part 76002.

  • I3C Advanced Target

    The complete target core, with a logic footprint you set. You get the controller's HDR-BT and multilane support, plus memory-mapped registers, DMA with flow control, and FIFO options on APB 3.0. Part 76016.

  • I3C Autonomous Target

    No local processor? This core runs data acquisition without one. Your application reads and writes a small register set. The core handles every exchange with the upstream controller over SDR, HDR-DDR and in-band interrupts. Part 76005.

  • Lite variants

    When silicon area is your tighter constraint, go Lite. The Lite Advanced Controller (part 70182) and Lite Advanced Target (part 70183) trim the footprint. They keep SDR, HDR-DDR, in-band interrupts and APB 3.0.

  • Why I3C

    You route fewer pins and signal paths than the I2C and SPI links it replaces. The bus runs faster at lower power, with built-in power management and less EMI at the interface. And your I2C devices don't have to go. They share the bus with the I3C ones.

Where I3C fits in your design

Part numbers, briefs and silicon

These I3C cores belong to Silvaco's PRO IP line, and every product in that line has been proven in production silicon.

  • 5I3C cores: two controllers, two targets and an autonomous target
  • V1.1.1MIPI I3C and I3C Basic compliance
  • 100 MbpsHDR-BT on the Advanced Controller and Advanced Target
  • 1, 2 or 4SDA lanes with multilane
  • Soft IPsynthesizable cores

Find your core by part number

Part number Core Supports
I3C
76002I3C 1.1 Advanced ControllerI3C V1.1, APB 3.0, SDR, DDR, HDR-BT, IBI, including I3C Basic
76005I3C 1.1 Autonomous TargetI3C V1.1, SDR, DDR, IBI, including I3C Basic
76016I3C 1.1 Advanced TargetI3C V1.1, APB 3.0, SDR, DDR, HDR-BT, IBI, including I3C Basic
70182I3C Lite Advanced ControllerI3C V1.1, APB 3.0, SDR, DDR, IBI, including I3C Basic
70183I3C Lite Advanced TargetI3C V1.1, APB 3.0, SDR, DDR, IBI, including I3C Basic
I2C
70026APB I2C Master/Slave ControllerI2C V2.1, APB 2.0, SMBus 2.0, ACCESS.Bus
Debug
70006IEEE 1149.7 JTAG ControllerIEEE Std 1149.7-2009, JTAG (IEEE 1149.1), 2-pin access, reduced scan time

SDR is single data rate. HDR-DDR and HDR-BT are the high data rate modes, and IBI is the in-band interrupt.

Size the core to your bus

Tell an IP specialist your chip's bus role, the data rates you need and the sensors on it. You'll hear which I3C IP core and configuration fit, how licensing works, and what integration takes on your process.

Talk to an IP specialist Download the I3C product brief (PDF)

I3C interface IP questions

MIPI I3C is the MIPI Alliance serial bus standard that brings I2C and SPI sensor links together on two wires. It adds dynamic addressing, in-band interrupts and high data rate modes on top. Silvaco's I3C interface IP meets MIPI I3C and I3C Basic version 1.1.1. You synthesize it into your own design as soft IP.

Pin count and signal paths both drop, and the bus runs faster and draws less power, with lower EMI. I3C also assigns addresses dynamically and carries interrupts in-band, so sensors don't need their own interrupt lines. HDR-BT tops out at 100 Mbps on Silvaco's Advanced Controller and Advanced Target, with multilane across up to four SDA lanes.

Yes. I3C is backward compatible with I2C, so your existing I2C sensors can stay on the same two wires. Silvaco's cores handle legacy I2C messaging and static I2C addresses. They also work with I2C pads fitted with a 50 ns glitch filter. The I2C parts you've already qualified can stay on the board.

The controller owns the bus. It assigns dynamic addresses, sends common command codes and starts every transfer. Targets answer it and can raise in-band interrupts when they have data. Silvaco's Advanced Controller can also take the secondary controller role. The Advanced Target runs HDR-BT across multiple lanes, just as the controller does.

It's a target that works without a local processor on its side of the bus. Silvaco's I3C Autonomous Target, part 76005, exposes a simple register set to your application. It manages the link to the I3C controller above it, using SDR, HDR-DDR and in-band interrupts. Data-acquisition designs with no MCU are the natural fit.

Both are built to MIPI Alliance specifications, but they do different jobs. The I3C cores are synthesizable controllers and targets for a two-wire sensor bus on standard I/O pads. Mixel's D-PHY, C-PHY and M-PHY are hard physical layers for high-speed camera, display and storage links. They're silicon-proven on 13 nodes at 9 foundries.

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