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Foundation IP: standard cells, memory compilers and interface IP

Foundation IP you license rather than build: standard cell libraries, memory compilers and I/O, characterized on named foundry processes and tuned to your PPA targets instead of a catalog average.

Talk to an IP specialist Download the IP catalog (PDF)

Foundation IP that bends to the chip

Most foundation IP ships as a fixed IP product, and your design absorbs whatever trade-offs came with it. Silvaco tunes cell sizing, memory configuration and the I/O ring to your target process and to the job the chip has to do.

  • Logic IP

    Many standard cell libraries on mature nodes predate tapless cells, clock gating and multi-bit flip-flops, and their power and area numbers show it. Silvaco's libraries carry 700 to 1,200 cells across multiple threshold voltages and track heights. Each cell family is sized down to the P/N ratio and every drive-strength step. You pick the variant that meets your power or speed target.

    28–180 nm · TSMC, GlobalFoundries, UMC · 10 CORE libraries, four with PMK and ECO kits

    Standard cell libraries

  • Embedded memory

    A memory sized for the average design fits neither a wearable nor an AI accelerator. The same Silvaco compiler can serve both, because the instance it generates follows the size and power options you set. Compilers cover single- and dual-port SRAM, register files and ROM.

    22–130 nm · TSMC, GlobalFoundries, UMC · 19 compilers

    Memory compilers

  • Interface IP

    Stock foundry I/O rarely matches the area, power and features your product needs. Silvaco's general-purpose I/O gives you programmable drive strength and slew rate, with ESD protection built in. The I/O team will also tailor the pad ring and ESD cells to your cost targets. Specialty I/O adds LVDS at up to 2 Gbps, SSTL, and I/O for cryogenic designs. Each core is designed to move between foundries, and it's verified before it lands in your integration flow.

    Ask an IP specialist which processes it's characterized on. For serializer and deserializer PHYs, see LVDS on the Mixel IP page.

    I/O IP

  • Low Power Foundation IP

    A battery-powered chip spends most of its life idle, so leakage decides how long your product lasts between charges. The low-power cells add power gating, multi-voltage design and level shifters. The single-port SRAM gets embedded power switches and read and write assist. Its retention, retention-nap and shut-down modes cut leakage one step at a time.

    Custom low-voltage characterization corners on request.

    Low Power Foundation IP

Coverage by line

Check your foundry and node against the Summer 2026 catalog. Not listed? Ask about a custom characterization.

Line Foundries Nodes Parts in the catalog
Standard cell librariesTSMC, GlobalFoundries, UMC28 to 180 nm10 libraries
Memory compilersTSMC, GlobalFoundries, UMC22 to 130 nm19 compilers

Library creation, migration and optimization reach beyond these IP products. Tell an IP specialist the node you're moving to.

The designs it goes into

  • SoC and ASIC development at mature and advanced nodesCustom SoCs, security and cryptographic processors, and audio and voice ASICs
  • Low-power mobile, IoT and wearable designsLow-leakage cells and SRAM power modes for edge devices, low-power DSP and Bluetooth Low Energy
  • Automotive and industrial SoCsIndustrial automation, process control and robotics, plus high-reliability automotive designs on established nodes with long-term supply
  • Display drivers and DDICsEmbedded memory compilers for display driver ICs

The record behind it

Every library and compiler in the catalog carries a foundry, a node and a part number you can quote in a qualification review.

  • 10 · 19standard cell libraries and memory compilers, each with its own part number
  • 35% · 20%less area and less power than off-the-shelf libraries, after Cello layout optimization
  • 4 million gates/mm²in a 28nm library built for density and low power
  • Liberty · LEF · GDSIIviews with every memory instance, DRC/LVS-clean and foundry-qualified
  • 25 yearsof SoC IP work at Dolphin Design before its memory compilers joined Silvaco

Bring your foundry and node

Say which library or memory you need and the PPA target it has to hit. An IP specialist will tell you what's characterized on your process today, what a custom characterization takes, and how licensing and evaluation work.

Talk to an IP specialist Download the IP catalog (PDF)

What buyers ask about foundation IP

Foundation IP, also called physical IP, is the set of pre-designed blocks a chip is assembled from. It covers standard cell libraries for logic, memory compilers for SRAM, register files and ROM, and the I/O at the chip's edge. Silvaco characterizes each block for a named foundry process and tunes it for power, performance, area and yield.

Logic IP is the standard cell library that synthesis and place-and-route turn into your digital logic, plus its power management and ECO kits. Memory IP comes as compilers. You set the size, ports and power modes, and the compiler generates an SRAM, register file or ROM instance to match.

Silvaco's current catalog lists standard cell libraries from 28 to 180 nm and memory compilers from 22 to 130 nm, at TSMC, GlobalFoundries and UMC. For interface and low-power IP, ask an IP specialist about your process. Custom characterization can extend coverage to nodes the catalog doesn't list.

Memory compilers generate fully characterized instances that pass DRC and LVS, with Liberty, LEF and GDSII views ready for your flow. Standard cell libraries come as CORE libraries in multiple threshold-voltage options, and four of the ten also ship power management and ECO kits. Custom PVT corners, including low-voltage operation, are available on request.

Yes, every memory instance is foundry-qualified and ships with characterized views. The standard cell libraries come with foundry-qualified views for their TSMC, GlobalFoundries and UMC processes. The memory compilers are silicon proven, with thousands of applications behind them at many foundries.

Often, yes, because Silvaco's library team creates, migrates and optimizes standard cell libraries on its Cello platform. For memory, the compilers generate instances sized to your area, power and speed targets. Whether a specific port makes sense depends on the foundry and process you're porting to.

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