Takes in
A SmartSpice netlist and your foundry models. Bring an HSPICE netlist with W-element RLGC matrix files, S-parameter model files, Verilog-A and AMS blocks, and C/C++ where you need it, plus technology-dependent parameters for dose rate. Device-level results from TCAD come in as I-V curves. Silvaco's own 22nm 6T SRAM upset case takes its transistor models from 3D Victory Device simulation.
- SmartSpice: the simulator RadHard is built on, reading the same netlist and models