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SmartDRC/LVS is Silvaco’s physical verification software. On analog, digital and mixed-signal IC layouts, it runs design rule checking, layout connectivity extraction and layout versus schematic comparison. It is silicon-proven and foundry certified at Tower Semiconductor, X-FAB and UMC. The tool began as POLYTEDA’s PowerDRC/LVS, sold since 2009. Silvaco acquired POLYTEDA in January 2021.
Your foundry’s rules, checked in a runtime you can plan a tapeout around.
You get design rule checks, layout versus schematic and netlist versus netlist. Special rules come included: antenna, density, pads, latches and more. Electrical checks flag shorts, opens and floating nets.
It handles device geometry drawn at any angle, and the same tool compares two layouts and generates fill layers. During extraction it calculates geometry-dependent device parameters, stress and well-proximity effects included.
One-Shot layout scanning combines rule checks in a single pass over each strip of layout. Runtimes stay predictable, and speed scales close to linearly as you add CPUs. On a foundry-certified 180nm deck it processes roughly 16 million transistors an hour, even flat.
Jobs split by rule group, layout strip and macro block, across one multi-core host or several. Scaling is proven to 128 cores, on Linux and Windows.
SmartRDE is where you set up a run and work through its results. Sort DRC violations by rule or cell, or filter them by area. Mark each one fixed or waived, and step through the hierarchy instead of a flat list.
LVS mismatches cross-probe to both layout and schematic. Filter them by cell, net or device type. In Expert, you browse errors natively, and every run leaves graphical and text reports.
You write decks in PWRL (pronounced “Power-L”), with variables, conditionals, macros and includes. Encrypt all of a deck, or only the part that needs protecting. Compile-only mode lets you debug a rule file before any layout runs through it.
Use it on its own or as part of Silvaco’s flow. It reads OpenAccess natively and connects to Expert and third-party layout editors.
Three inputs go in. A checked layout comes out, ready for extraction.
A layout, the schematic netlist it should match, and a rule deck. Layouts arrive as GDSII, OASIS or OpenAccess; netlists as SPICE, CDL, Verilog or OpenAccess; rules as PWRL.
The layout editor for fixes, then extraction.
Using another layout editor? KLayout, LayoutEditor and Symica DE integrations ship with the tool. Integrations for Cadence Virtuoso, Synopsys Laker, NI AWR Analog Office and TexEDA LayTools are available on request.
From memory arrays to layouts the size of a display panel.
An evaluation usually opens with two questions: has a foundry put it to work, and where’s the datasheet?
Tower’s Ofer Tamir, Managing Director of CAD, Design Enablement and Support, on qualifying its iPDK and SPICE models with Silvaco’s flow. Tower is the lead analog foundry for that work, with SmartDRC and SmartLVS in the flow.
Power-device layouts are full of curved shapes, the geometry DRC engines tend to struggle with. The session shows Expert drawing them and SmartDRC checking them, without giving up speed or accuracy.
Where SmartDRC/LVS came from. POLYTEDA optimized its technology for analog mixed-signal, digital, MEMS, memory, photonics, power management, radiation-hardened and RF designs.
Two pages on DRC, ERC, LVS, layout versus layout, fill and the PWRL rule language. It also covers parallel runs, SmartRDE debugging and the formats the tool reads.
Tool structure, batch runs, SmartRDE and parallel processing. Then LVS results on large chips, PWRL examples, editor integrations, and rule decks by foundry and node.
Run DRC, LVS, netlist versus netlist, XOR and fill generation from the command line. Each job is set up in a run configuration file.
Bring a layout and the rule deck your foundry gave you, and watch SmartDRC/LVS run it. Silvaco EDA already runs at six of the world’s ten biggest semiconductor companies.
Physical verification is the check a finished IC layout has to pass before it goes to the foundry. Every shape must meet the design rules. The wiring must still match its schematic, and nothing can be shorted, open or floating. It is the final gate before mask creation, and SmartDRC/LVS is Silvaco’s tool for it.
DRC asks whether the layout can be built: widths, spacings, enclosures, density and antenna limits from the foundry’s rules. LVS asks whether it is the circuit you designed. It extracts devices and connections from the layout and compares them with the schematic netlist. A layout needs to pass both, and SmartDRC/LVS runs both.
Tower Semiconductor, X-FAB and UMC have certified it for their processes, and it is silicon-proven. Rule decks also exist for processes at other foundries, among them ams AG, IHP, SkyWater and Vanguard. Check the PDK table first. Then ask us about your exact node: is there a deck, and is it sign-off grade?
It parallelizes across rule groups, layout strips and macro blocks at once. In one test, a 660 MB flat layout ran against a 180nm foundry-certified deck: 64 CPUs finished about ten times faster than one, and going from 32 to 64 still gained over 25%. Turbo mode trims runtime further on most designs, at minimal cost to accuracy.
Netlist versus netlist (NVN) compares two netlists directly, with no layout involved. Think of a schematic against an earlier extraction, or two revisions of one design. SmartDRC/LVS runs NVN flat, hierarchically, or with subcircuits treated as black boxes. The black-box option lets you bring verified IP blocks in at the top level.
Yes. It runs standalone as well as inside Silvaco’s flow. KLayout, LayoutEditor and Symica DE work with it out of the box. For Cadence Virtuoso, Synopsys Laker, NI AWR Analog Office or TexEDA LayTools, ask for the integration. Decks written in SVRF for Calibre need converting, because PWRL is a different language and keywords don’t map one to one.