Support portal Careers Contact Investors
EN
EN · English JA · 日本語 KO · 한국어 ZH · 简体中文
Request a Demo
Request a Demo
Request a Demo
Support portal Careers Contact Investors
Language EN JA KO ZH

Jivaro Pro: parasitic reduction for post-layout SPICE simulation

Jivaro Pro cuts an extracted parasitic network down before you simulate it, so post-layout SPICE runs finish sooner, at an accuracy you set yourself.

Talk to our Technical Experts Documentation

What Jivaro Pro does

Jivaro Pro applies patented mathematical parasitic reduction to the network extraction leaves behind. Circuit complexity drops until your post-layout SPICE simulation finishes, up to 15X faster. How much accuracy you trade for that speed is your call, not a setting fixed inside the tool. Design teams at IDMs and fabless chip companies around the world run it. Because it stands alone, it sits between your extractor and your simulator, whichever ones they are.

Capabilities

You decide how hard the netlist gets cut, and where.

  • Reduction

    Model order reduction, a patented mathematical approach, shrinks the parasitic network within the tolerance you choose. Start in automatic mode, which adapts to your design, or take over any of more than 30 parameters when you want the speed-accuracy balance in your own hands.

    Aim reduction at single nets, whole subcircuits or paths anywhere in the hierarchy, and give each its own threshold. You can also merge multi-finger devices and strip out dummy structures, then configure and review it all in a GUI.

  • Coverage

    R, RC, RCC, RLC and RLCK networks, with controlled sources. Netlists extracted across multiple corners reduce too, and so do parasitic networks that change with temperature.

    Power nets and metal fills can stay in your simulation, adding accuracy without the runtime they'd normally cost.

  • Formats

    Bring DSPF, SPEF, SPICE3, HSPICE or Spectre netlists, Calibre View parasitic netlists, or OpenAccess databases.

    Technology nodes down to 2nm.

  • Independence

    Jivaro Pro isn't tied to any extraction or simulation tool. It plugs into your current flow and runs next to the major EDA suites.

    Reduction built into an extractor or simulator follows fixed rules. Here, the strategy stays with you. It runs on Red Hat Enterprise Linux 7.9 and 8 and SUSE Linux Enterprise Server 12.

Works with

Your extracted netlist goes in. A smaller one comes out, ready for your simulator.

Takes in

Any extracted parasitic netlist, whatever tool produced it.

Hands off to

A reduced netlist for your post-layout run.

  • SmartSpice, or a third-party SPICE simulator, takes the reduced netlist for post-layout simulation. SmartSpice also has the Jivaro reduction engine built in, configured from its own options.
  • Viso, for analyzing the parasitic network before or after reduction.

Applications

The post-layout runs that usually hold a schedule up.

  • Blocks that won't simulate in fullRun the post-layout simulation that wouldn't finish on the netlist as extracted, including ones that used to be out of reach.
  • Simulations with power nets and metal fillsInclude them for accuracy. The reduced netlist keeps the run time in check.
  • Multi-corner and temperature-dependent workCorner sweeps and temperature-dependent parasitics, reduced like any other netlist.
  • More coverage in the same compute budgetRun more simulations without adding CPUs or memory.

Proof and resources

See what design teams measured on their own blocks.

  • CustomerMay 2025

    Alps Alpine

    Alps Alpine, which makes sensors and electronic components, adopted Jivaro Pro to speed up development of the ICs inside its high-precision sensor products.

    “The introduction of Jivaro Pro is consistently reducing post-layout SPICE simulation run times while maintaining accuracy, with at least a 5X improvement observed at the 40nm and 55nm nodes.”

    Yasuyuki Hattori, Senior Manager of IC Engineering Dept. Engineering Headquarters at Alps Alpine Co., Ltd.

  • Customer

    eTopus

    eTopus builds ultra-high-speed mixed-signal IP for high-performance computing and data centers. On its FinFET flow, full post-layout runs on large blocks were taking weeks.

    “…a full simulation on one of our blocks would run 20+ days. After using Jivaro Pro this runtime was reduced to 6 days while maintaining the designer’s accuracy requirements.”

    Harry Chan, Founder and CEO, eTopus

  • Customer talk · SURGE 2025

    Silicon Creations

    Chung-Chun Chen, Director of Analog Design, shows how Jivaro Pro speeds up verification of high-frequency analog mixed-signal components.

  • Product brief · PDF

    Jivaro Pro – Parasitic Reduction for Fast, Accurate Simulation

    Measured speedups of 2.2X to 15.2X on designs from 130nm to 7nm, with what it reduces, how targeting works, inputs and supported platforms.

  • Presentation · PDF

    Jivaro Pro – Parasitic Reduction for Fast, Accurate Simulation

    Speedups from 2.2X to 15.2X across design types and nodes from 130nm to 7nm, targeted reduction by net, and device merging.

  • Application note · PDF

    SmartSpice HPP: High Performance Parallel with SPICE Accuracy

    How parallel SmartSpice handles post-layout runs, and how to set up Jivaro reduction from inside it.

  • Webinar

    Advances in Parasitic Pro Reduction and Analysis with Jivaro and Viso

  • Webinar

    Accelerate the Circuit Simulation Flow with Jivaro Parasitic Reduction

All parasitic extraction application notes

Start with your slowest post-layout run

Tell us which block takes longest to simulate after extraction. Our engineers will show you how much runtime Jivaro Pro takes off it, and what that costs in accuracy.

Talk to our Technical Experts Documentation Support and Downloads

Questions about Jivaro Pro

Parasitic reduction, sometimes called RC reduction, shrinks the resistor, capacitor and inductor network that extraction adds to a post-layout netlist. Most of those elements go, and the netlist's electrical behavior stays within the error budget you give it. Jivaro Pro does this with model order reduction, a patented mathematical method, instead of dropping small parasitics by rule.

Up to 15X faster post-layout SPICE simulation, with published results from 2.2X to 15.2X depending on the design and node. Alps Alpine reports at least 5X at 40nm and 55nm, and eTopus cut one block's full simulation from more than 20 days to 6. What you get depends on your design.

Only as much as you allow. Automatic mode picks a balance for your design, and more than 30 parameters let you set it yourself, net by net if you need to. You can hold critical nets to strict accuracy and reduce power nets aggressively, all inside the same netlist.

Yes. Jivaro Pro takes the output of any extraction tool and passes its reduced netlist to SmartSpice or any third-party SPICE simulator, so nothing else in your flow has to change. Inputs can be DSPF, SPEF, SPICE3, HSPICE, Spectre or Calibre View netlists, or OpenAccess databases.

DSPF, SPEF, SPICE3, HSPICE and Spectre netlists, Calibre View parasitic netlists, and OpenAccess extracted views. Inside those files, Jivaro Pro reduces R, RC, RCC, RLC and RLCK networks with controlled sources, and it handles multi-corner and temperature-dependent extractions too. Full power networks can be reduced alongside the signal nets.

Jivaro Pro is listed for technology nodes down to 2nm, and customers run it on planar and FinFET flows alike: Alps Alpine at 40nm and 55nm, eTopus on FinFET. Silvaco's published speedup results cover designs as mature as 130nm and as advanced as 7nm.

Related

All of AI-Driven Design