Products & Workflows
Process and device physics, from simulation to the fab floor
EDA tools, licensed IP, verification and enablement
Why Silvaco
Solutions
Resources
TCAD
Analog and Custom Design
Parasitic Extraction
SPICE Simulation
Variation and Yield
The Simulation Standard
Technical journalFoundry support
Process Design KitsSupport and Downloads
Partners
TCAD
Lithography
Plasma
Circuit Simulation
Analog and Custom IC
Design IP
At multi-million-element scale, an SRAM array or a TFT display panel can outgrow full SPICE: the transient run won't finish in time to matter. SmartSpice Pro is the FastSPICE simulator for those designs. It pairs fast-SPICE partitioning with the traditional SPICE algorithms that hold results close to SPICE accuracy. And because it's integrated with SmartSpice, your DC operating point and transient runs use the models you already trust.
A fast result is only worth having if you know what it did to get there, and you can turn accuracy back up where a block needs it.
Multi-rate, event-driven transient simulation. Active and latent partitions talk through events, so the quiet parts of your circuit aren't solved at the rate of the busy ones.
Adaptive timestep control and discrete time grid mapping do the work underneath, with traditional SPICE algorithms kept wherever accuracy depends on them.
Partitions form from MOS channel-connected components. Power blocks are detected automatically, floating-capacitor coupling and feedback loops get dedicated handling, and linear RCL clusters are found and exploited instead of solved like any other partition.
You control activity, latency, coupling and accuracy per partition, or reach for composite option sets and tune the whole run at once.
Analytical FinFET, BSIM3v3, BSIM4, BSIMSOI, TFT, HiSIM and PSP models, plus lookup tables for BSIM3v3 and BSIM4. Device models are HSPICE and Spectre compatible.
Verilog-A for behavioral blocks, and TSMC's TMI modeling interface.
DC operating point and transient, on a scalable fast parallel linear solver, with flows for bisection optimization and Monte Carlo analysis.
Designer-oriented post-processing functions let you sanity-check a result before you rely on it.
You bring the netlist and foundry models you already have. The results go straight into waveform analysis.
A netlist, a model set and partitioning controls. Netlists in SPICE, HSPICE or Spectre form, with Verilog-A blocks. The HSPICE or Spectre models your foundry supplies. And the controls that decide how the circuit splits and how much accuracy each partition keeps.
Waveforms, measurements and a log. Results come out as FSDB waveforms alongside measurements, a log file and analysis results, and open in SmartView for viewing and analysis.
If full SPICE is still running when you need the answer, your circuit probably looks like one of these.
Silvaco EDA already runs at six of the ten largest semiconductor companies, so you won't be the first team to trust it. The TFT panel comparisons against SmartSpice are the ones worth repeating on your own circuit.
"We decided to use SmartSpice Pro in order to be able to release high functionality, high value-added optical sensors in a short period of time. As a result, we have been able to further improve both design efficiency and design quality."
Hiroyuki Fukui, IC Design Division Senior Manager, KODENSHI CORP.
Partitioner inputs and outputs, simulation controls, a waveform overlay against SmartSpice, and where SmartSpice Pro sits on accuracy and speed across the SmartSpice line.
Why a TFT panel with millions of devices and a very uneven signal activity profile pushes full SPICE past practical limits, and how a FastSPICE run handles it.
A TFT-based display panel simulated in SmartSpice Pro, with result accuracy compared against SmartSpice and the performance and accuracy controls walked through.
Silvaco's display design tools as shown at Display Week 2019, and where SmartSpice Pro fits among them.
SmartSpice Pro gains external sampling, .LET statements and improved .option autostop support.
The release that improved SmartSpice Pro's bisection and Monte Carlo flows, its partitioning algorithms and its PWL source support.
Manuals, worked examples and release notes for every tool family, Circuit Simulation included.
Bring the array or panel that's stalling full SPICE, plus a SmartSpice run you trust on a piece of it. An application engineer works through the comparison with you.
FastSPICE is circuit simulation built for capacity. Instead of solving every device at every timestep, it partitions the circuit, updates quiet partitions less often and lets events carry changes between them. That's how multi-million-element memory and display circuits finish in practical time. SmartSpice Pro is Silvaco's FastSPICE simulator.
Use SmartSpice Pro when the circuit is a large SRAM array, a TFT display panel or another multi-million-element block, and a full SPICE transient run won't finish in time. Use SmartSpice for AC or noise analysis, for accuracy-critical analog blocks, and for any run you need at full SPICE accuracy. Both read the same models.
That depends on the circuit and on how you set the controls. SmartSpice Pro keeps traditional SPICE algorithms where accuracy depends on them, and you can tighten accuracy for one partition or for the whole run. To see the trade-off on your design, compare it against a SmartSpice run on a piece of the same circuit.
Analytical FinFET, BSIM3v3, BSIM4, BSIMSOI, TFT, HiSIM and PSP models, with lookup tables for BSIM3v3 and BSIM4. FinFET support covers 7, 10 and 16 nm technologies. Behavioral models come in through Verilog-A, and SmartSpice Pro also supports TSMC's TMI modeling interface for foundry models that use it.
Yes. SmartSpice Pro works with HSPICE- and Spectre-compatible device models and reads SPICE, HSPICE and Spectre netlists. SmartSpice uses the same foundry models, so one model set covers a block whether it runs in full SPICE or in FastSPICE. You don't keep two libraries in step.
Each partition gets its own activity, latency, coupling and accuracy controls, plus event-driven resolution control. Composite macro options set global accuracy and performance in one step when you'd rather not tune partition by partition. Adaptive timestep control, discrete time grid mapping and Newton-Raphson block solution control sit underneath.