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Give a SPICE simulator your netlist and a compact model for every device, usually from the foundry's PDK. It solves for the voltage at every node and the current in every branch, at a bias point, across frequency or step by step through time. What comes back is a waveform, and the waveform is your design review.
You can abstract a digital gate into a delay. You can't do that with a bandgap, a PLL or a data converter. They pass or fail on offsets, noise and bias currents that only exist at the transistor. So analog sign-off is still a SPICE simulation run, and the models you feed in matter as much as the solver.
An SRAM array or a display panel holds millions of devices, and solving each one at every timestep stops being practical. So you spread the work across cores, or partition the circuit and let its quiet parts run on a coarser schedule. SmartSpice handles the first. SmartSpice Pro handles the second.
The parallel SPICE simulator for circuits where the full transistor-level answer decides sign-off, running your HSPICE and Spectre decks.
SmartSpice circuit simulatorFastSPICE for SRAM and TFT display circuits that run to millions of devices, where capacity matters more than solving each one in full.
SmartSpice Pro FastSPICEWaveform viewing and measurement for analog, RF, digital and mixed-signal results, live during a run or after it.
SmartView waveform analysisRadiation analysis built on the SmartSpice engine, covering single-event effects and dose rate.
SmartSpice RadHard radiation simulationIR drop, electromigration and thermal analysis on analog and mixed-signal designs, from one block to the full chip.
InVar IR-drop and thermal analysisA SmartSpice capability
Tune model and instance parameters while the circuit runs, and watch the waveform follow each change.
Circuit Rubberband real-time tuningIt comes down to what your circuit can tolerate, an approximation or its own size. Both read the same foundry models, so the choice never means rebuilding your flow.
Full SPICE accuracy
Choose SmartSpice when only the transistor-level answer is acceptable: a critical net, a precision analog block, custom digital logic or a cell library you're characterizing. You get DC, AC, transient and noise analysis with built-in local and global optimization. Several solvers and stepping algorithms work toward convergence, on circuits of more than 8 million active devices.
SmartSpiceFastSPICE capacity
SmartSpice Pro is the pick once a circuit runs to millions of elements and most of them repeat, as in an SRAM array or a TFT panel. Active and latent partitions run at different rates, with accuracy set per partition. It covers DC operating point and transient, so AC and noise stay in SmartSpice.
SmartSpice ProNeed something in between? SmartSpice's HPP mode runs a transient simulation in parallel across your cores for fast-analog speed, and the accuracy tolerances stay yours to set.
Your HSPICE and Spectre decks load in SmartSpice, which supports their analysis features and result formats. Legacy PSPICE and Berkeley SPICE netlists work as well, so SmartSpice can sit next to the simulators you already have.
Foundry-supplied HSPICE and Spectre models load directly in SmartSpice and SmartSpice Pro, and you can draw on calibrated model libraries for TFT, OTFT, SOI, HBT, FRAM and FinFET technologies. Custom models come in through Verilog-A, covering the analog features of Verilog-AMS 2.3.1. SmartSpice Pro also supports TMI.
Check the PDK table for your foundry and nodeSmartSpice runs inside Cadence ADE in Spectre-compatible mode, and it reads the HSPICE netlists and models a Synopsys flow produces.
Send jobs through LSF or Sun Grid, and SmartSpice spreads Monte Carlo and .ALTER runs across your network CPUs. SmartView opens the results, including FSDB, Spectre PSF, Touchstone and Liberty data.
Silvaco EDA already runs at 6 in 10 of the largest semiconductor companies, so you won't be the first team to put it to work.
Mobile Semiconductor moved its memory-compiler characterization to SmartSpice and SmartView. One 22nm node took 56,000 SPICE runs, characterization times improved by 50%, and the team's legacy control files and .MEASURE statements carried across.
The move from 5.0.3.R to 5.2.0.R brought a new solver with speedups of up to 25x. It also added an improved GUI, a built-in text editor, SmartSpice RF and Pro updates, and better Spectre compatibility inside Cadence ADE. SmartSpice currently ships as 5.9.2.R.
In Silvaco's comparison run, 5.0.3.R finished in 1,124 seconds against 4,766 for 4.44.3.R, using about a ninth of the memory.
On a post-layout 45nm SRAM, HPP with Jivaro reduction and Turbo mode cut a run from about 90 hours to 2.2 hours, with power measurements within 1%. The note covers setup for pre- and post-layout work.
Why a four-terminal TFT model matters for display backplanes, and how Flex Modeling reproduces image retention at SPICE level.
Where single-event upsets come from, how the Messenger current model represents a particle strike, and how a .RAD statement applies it in SmartSpice.
Product briefs (PDF): SmartSpice · SmartSpice Pro · SmartView · SmartSpice RadHard
Bring the circuit that's giving you trouble: the deck, the foundry models, the transient that won't converge. Talk it through with a Silvaco applications engineer.
Installers, release notes and manuals are in the Silvaco customer portal, which needs an account. SmartSpice, SmartView and Gateway come together in the IC Design package of the 2025 baseline release.
Open a support case, or get help with licensing and installation.
SPICE simulation predicts how a circuit behaves by computing every node voltage and branch current from a netlist and compact device models. It works at a DC operating point, across frequency or through time. Analog and mixed-signal sign-off still relies on it, since no higher-level abstraction captures a bandgap's offset or a PLL's jitter.
SPICE solves every device at every timestep, which is accurate but caps the circuit size you can run. FastSPICE partitions the circuit and simulates inactive parts less often, trading a controlled amount of accuracy for capacity. Silvaco's FastSPICE engine is SmartSpice Pro, built for multi-million-element memory and display circuits.
It depends on the circuit. SmartSpice fits work where accuracy decides the outcome, SmartSpice Pro fits large SRAM arrays and TFT panels, SmartSpice RadHard covers radiation effects and InVar covers IR drop and thermal. SmartView is the waveform viewer across the whole SmartSpice line.
Yes. SmartSpice plugs into Cadence ADE as the simulator, in Spectre-compatible mode. In a Synopsys flow the connection is through formats: HSPICE decks and models load into SmartSpice, HSPICE and FSDB waveforms open in SmartView, and the setup you already run stays in place.
SmartSpice reads HSPICE, Spectre, PSPICE and Berkeley SPICE netlists, plus foundry HSPICE and Spectre models including BSIM3, BSIM4, BSIM6 and BSIM-CMG for FinFET. Verilog-A handles custom and behavioral models, and SmartSpice Pro adds TMI. On the results side, SmartView takes SmartSpice raw files, HSPICE, Spectre PSF, FSDB, Touchstone and VCD.
A particle strike or a dose-rate pulse injects current your circuit was never designed to carry. SmartSpice RadHard builds that physics into compiled versions of standard device models instead of added subcircuits. You call the analysis with a .RAD statement and run it on the foundry models you already have, with no netlist edits.