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Gateway is Silvaco's schematic editor for integrated circuit design. You capture analog, RF, digital and mixed-signal circuits in one hierarchical schematic, and Gateway generates every view the rest of the flow reads. Where you start decides how many handoffs follow. Start here, and the circuit you drew is the one SmartSpice simulates, Expert lays out and SmartDRC/LVS checks. Flat or hierarchical, in any process technology. Designs from other schematic editors come in through OpenAccess or EDIF.
Built for designs too big for one sheet, and for teams that share them.
Work across multiple views and sheets in one hierarchy, however large the design gets. Wires and busses are edited where they sit, including ripping a bus apart or merging several into one.
Connect by wire, by pin or by net name, or let implicit, global and inherited connections do it for you. Naming rules for busses, instances and nodes keep a big design readable.
Set your own electrical and drawing rule checks, and Gateway flags netlist violations before they reach the simulator. Minimum and maximum limits on parameters catch a mistyped value the moment you enter it.
Show device parameters, DC bias and thresholds right on the schematic, down to each MOS device's operating region, at any level. View Info follows a signal from level to level, and cross-probing ties every net to its waveform.
One schematic writes SPICE, CDL, NDL and Verilog (IEEE 1364) netlists, plus HSPICE-compatible input decks.
It works with OpenAccess and iPDKs, and trades schematics with third-party editors using EDIF 2 0 0. Only have a SPICE or Verilog netlist? Gateway draws the symbols from it.
JavaScript, extended with around 200 Gateway functions, lets you reshape menus and the interface around how your team works, and add callback symbols of your own.
Callbacks evaluate expressions as you edit: design rules, tolerances, parametric calculations, process skews.
Encrypt what shouldn't be exposed, whether that's your own IP or a third party's block inside your design.
A design kit can ship encrypted netlists behind its symbols, so the people you give a block to can use it without opening it.
However a design starts, the same schematic feeds every tool after it.
A circuit drawn in Gateway, or a netlist you already have. Point Gateway at a legacy SPICE or Verilog netlist and it generates the symbols. Schematics from other editors arrive through OpenAccess or EDIF 2 0 0.
Third-party inputs: OpenAccess and EDIF 2 0 0 schematics, and iPDK foundry kits.
Every tool downstream reads the one schematic.
From a single standard cell to an LNA and mixer.
Two companies have put their names to Gateway publicly. The datasheet, the slides and the app notes open with no form to fill in.
The Taiwan-based silicon and silicon carbide power device maker has committed long term to Silvaco for its SiC work. Victory Device covers the device side; Gateway and SmartSpice cover the circuit.
“The combination of Victory Device, Gateway, and SmartSpice provides us with a comprehensive solution that bridges the gap between process development and circuit design…”
Dr. CS Chang, President, APEC
The analog and mixed-signal IP supplier runs Gateway with Expert and SmartView in its most advanced FinFET flow, for IP in production from 7 to 180 nm.
Two pages: editing features, the netlists it writes, and how it connects to SmartSpice, SmartView and Expert.
Schematic-driven layout with Expert, SmartDRC/LVS cross-probing, the symbol generator, and simulation results written back onto the schematic.
A five-stage current-starved VCO, taken from a Gateway schematic to SmartSpice across three corners of a 0.18 µm UMC process.
Drop a Verilog-A behavioral model into a schematic as a subcircuit. A D flip-flop simulates about ten times faster than at transistor level.
Send a schematic or a legacy netlist from your current flow, and our application engineers will capture, netlist and simulate it in Gateway. You'll see the tool work on the design you actually have to tape out.
A schematic editor is the tool where you draw a circuit as symbols and wires, then turn the drawing into netlists for simulation and layout-versus-schematic checks. In IC design, it's where the flow begins. Silvaco's is Gateway, which handles RF, analog, digital and mixed-signal circuits, flat or hierarchical.
Four formats come out of one schematic: SPICE, CDL, NDL and Verilog (IEEE 1364), covering simulation, LVS and layout. Gateway also produces HSPICE-compatible input decks. It also works in reverse, turning a SPICE or Verilog netlist into symbols, and swaps schematics with other editors through EDIF 2 0 0 or OpenAccess.
Yes, HSPICE: Gateway writes HSPICE-compatible input decks. Within Silvaco it also drives SmartSpice, the Silos Verilog simulator and the TCAD device simulators. No integration with any other simulator environment is published, so if your flow relies on one, raise it with our application engineers before an evaluation starts.
Yes. Gateway supports OpenAccess and interoperable PDKs (iPDKs), so a foundry kit written for OpenAccess tools works from your schematic onward. Silvaco also maintains an extensive set of its own custom PDKs. Kits change as foundries release new ones, and the Process Design Kits page lists what's current for your foundry and node.
Through Expert, Silvaco's layout editor. Gateway passes connectivity to Expert and drives its automatic placement, and Expert keeps each device where its symbol sits relative to the others. You can cross-probe between the schematic, the layout and SmartDRC/LVS results. Expert can also start from a SPICE or CDL netlist instead.
Yes. Silvaco's encryption covers your own IP and any third-party IP inside a design. Design kits go a step further. A symbol can hide an encrypted netlist, so the team or customer you hand a block to can simulate it without ever reading the netlist behind it.