SPICE Simulation Application Notes

24 application notes for analog, mixed-signal and RF circuits, on SmartSpice, SmartView, Gateway, Verilog-A modeling, Utmost IV extraction, single-event upset and EDIF import.

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General 10 notes

Top 10 New Features in the SmartSpice 2022 Baseline ReleasePDF, 2.0 MBOpen
Top 10 New Features in the SmartSpice 2021 Baseline ReleasePDF, 491 KBOpen
SmartSpice HPP: High Performance Parallel with SPICE AccuracyPDF, 893 KBOpen
SmartSpice: Built-in Interconnect RC Network ReductionPDF, 800 KBOpen
Managing Circuit Simulation Using VWFPDF, 2.6 MBOpen
SmartSpice Circuit Design Using Local and Global OptimizationPDF, 1.0 MBOpen
Interactive Measurement in SmartViewPDF, 3.0 MBOpen
Performing Operation Point Analyses with Variable SweepsPDF, 1.2 MBOpen
Simulating Circuits with Parasitics and RCL ReductionPDF, 931 KBOpen
Schematic Driven Process Corners AnalysisPDF, 1.4 MBOpen

Verilog-A Applications 6 notes

Introduction to VA-DebuggerPDF, 1.0 MBOpen
New Syntax for running VerilogA Models in Gateway/SmartSpicePDF, 807 KBOpen
Get the Best Performance From Your Verilog-A ModelPDF, 663 KBOpen
Debugging Verilog-A Flow Under WindowsPDF, 559 KBOpen
Know More About Verilog-A Parser in SmartSpicePDF, 616 KBOpen
Using Verilog-A to Simplify a NetlistPDF, 605 KBOpen

Modeling and Utmost IV 3 notes

Utmost-IV Delivers Full Capability of RPI TFT ModelsPDF, 7.4 MBOpen
HiSIM_HV Single Geometry Parameter Extraction with Automated Utmost-IV OptimizationPDF, 930 KBOpen
Guide To Utmost IV OptimizersPDF, 604 KBOpen

Single-Event Upset Applications 2 notes

SmartSpice SEU ModulePDF, 771 KBOpen
Physical 3D Single Event Upset Simulation of a SRAM Cell with Victory and SmartSpice SEEPDF, 961 KBOpen

EDIF Import 3 notes

EDIF 2 0 0 – Conversion Guidelines for Importing Legacy EDIF Files for First-time UsersPDF, 276 KBOpen
Importing Standard design Libraries using EDIF 2 0 0PDF, 389 KBOpen
Salvaging Old Designs Through EDIF 2 0 0PDF, 273 KBOpen

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SPICE Simulation Application Notes

General 10 notes

Verilog-A Applications 6 notes

Modeling and Utmost IV 3 notes

Single-Event Upset Applications 2 notes

EDIF Import 3 notes

More from the Technical Library

Also in SPICE Simulation

Application notes for other product lines

Got a question the paper didn't answer?

SPICE Simulation Application Notes

General 10 notes

Verilog-A Applications 6 notes

Modeling and Utmost IV 3 notes

Single-Event Upset Applications 2 notes

EDIF Import 3 notes

More from the Technical Library

Also in SPICE Simulation

Application notes for other product lines

Tools these notes cover

Got a question the paper didn't answer?