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Design IP: Production-Ready Offerings for Production-Ready SoCs

Production-Ready Offerings (PRO IP) for SoC designs, characterized for specific foundry processes and available to license now: Mixel mixed-signal interface IP, standard cell libraries, memory compilers, AMBA, I3C and automotive networking IP.

Don't see what you need? Talk to the IP team.

Why license PRO IP

Most of a chip is built on standards: interfaces like MIPI, I3C and AMBA, and building blocks like standard cells and memory compilers. Designing them in-house takes design, verification and foundry characterization but rarely sets a chip apart. PRO IP lets your team spend that effort where it does.

  • Time to market

    PRO IP is characterized for specific foundry processes and delivered with the views your flow needs, so integration starts right away instead of after a block development cycle.

  • Lower risk

    PRO IP is production-ready on the processes listed below, and the Mixel product line is silicon-proven on 13 nodes at 9 foundries. Support continues from integration through production.

  • Focus where it matters

    Owning a block in-house means engineering, verification, foundry characterization and support for every process variant, long after tape-out. Developing and maintaining IP across processes is what we do, so your team doesn't have to.

Find the IP for your design

PRO IP covers interface, foundation and system IP. Coverage by foundry and node differs by product line, and the table below lists it for each one.

Mixel interface IP

Silvaco's Mixel product line covers MIPI D-PHY, C-PHY and M-PHY, C-PHY/D-PHY and LVDS/D-PHY combos, LVDS, and ASA Motion Link. Mixel IP is silicon-proven on 13 nodes at 9 foundries, and Mixel was the first IP provider to demonstrate silicon-proven MIPI D-PHY, C-PHY and M-PHY. Mixel was founded in 1998 and joined the MIPI Alliance in 2006.

Explore Mixel IP

Foundation and system IP

Libraries and compilers characterized per foundry process, plus synthesizable cores for the logic that ties them together.

  • Foundation IP

    Pick the track height and Vt mix your design needs instead of settling for one fixed library. The standard cell range covers 28 to 180 nm; SRAM, ROM and register-file compilers cover 22 to 130 nm, all enabled at TSMC, GlobalFoundries and UMC. Low Power Foundation IP, GPIO and LVDS I/O complete the line.

    Foundation LVDS I/O is transmitter and receiver cells at the pad, for the I/O ring. The Mixel LVDS PHY is a separate product for display links.

  • AMBA IP cores and subsystems

    AXI, AHB and APB controllers, plus the bus fabrics and bridges that join them. The pre-integrated subsystems include a secure one built for IoT. Synthesizable, so no node lock-in.

    See AMBA IP
  • Automotive networking IP

    FlexCAN, MultiCAN, LINFlex and FlexRay controllers for ASIL-B functions such as steer-by-wire and brake-by-wire.

    Mixel automotive PHYs: ASIL-B D-PHY, ASA Motion Link.

    See Automotive networking IP
  • I3C interface

    I3C cores for sensor buses that need speed on few pins. They support in-band interrupts, run at low power and keep your existing I2C devices on the same bus.

    See I3C IP

Silvaco IP outside PRO IP

  • Embedded processors

    The M8051EW for low-power 8-bit control, and ColdFire V1, V2 and V4 at 32 bits, as cores or full processor platforms.

    See Embedded Processors
  • Power management

    Two LDO regulators, rated 30 mA and 250 mA, with outputs adjustable from 0.45 to 0.9 V. A 0.45 V bandgap reference completes the set. All three run on TSMC N3P.

    See Power Management IP
  • Other IP

    An IEEE 1149.7 TAP controller: JTAG debug over two pins, with shorter scan times.

    See Other IP

IP management

Software that tracks the IP you license, the IP you build, and where each one ends up.

  • IP Grid

    IPVault is where your IP lives: cataloged, stored and handed out, with support tickets and license records alongside. IPAudit tells you which IP sits inside a given SoC design.

    See IP Grid
  • Xena IP Management

    One record for the business and engineering sides of your IP. Xena keeps an enterprise catalog, locks release versions and ties access to license terms.

    See Xena

Check your foundry and node

AMBA, I3C and the automotive networking controllers are soft IP, synthesized onto the node you choose. Hard IP is characterized per process, so your foundry and node are the first filter. The table lists PRO IP, available to license now.

PRO IP by product line, with its label, foundries, process nodes and the page or table it links to
Product line Label Foundries Process nodes Links to
C-PHY/D-PHY comboMixel IPTSMC, STMicroelectronics2 nm to 65 nm
D-PHYMixel IPTSMC, GlobalFoundries, Samsung, SMIC, Tower, UMC7 nm to 90 nm
C-PHYMixel IPTSMC22 nm and 40 nm
M-PHYMixel IPTSMC40 nm
LVDS/D-PHY comboMixel IPGlobalFoundries, TSMC, Tower22 nm to 65 nm
LVDSMixel IPTSMC, UMC40 nm
ASA Motion LinkMixel IPTSMC22 nm
Standard cell librariesFoundation IPTSMC, GlobalFoundries, UMC28 nm to 180 nm
Memory compilersFoundation IPTSMC, GlobalFoundries, UMC22 nm to 130 nm

Don't see your foundry or node? More IP is in active development and may meet your needs. Talk to the IP team. Memory compilers can be characterized to custom PVT corners on request.

Proof and resources

Proof

  • 13 nodes, 9 foundriesSilicon-proven Mixel IP.
  • 1 billion+Units shipped with Silvaco automotive networking controllers.
  • ISO 26262, ASIL-BAutomotive IP for ASIL-B applications, with ISO 26262 functional safety support across MIPI, ASA and CAN.
  • Liberty, LEF, GDSIIFully characterized, DRC/LVS-clean instances with Liberty, LEF and GDSII views.
  • ISO 9001Certified quality management across Silvaco TCAD, EDA and IP products.

Resources

Bring your foundry, node and block list

Tell the IP team what you're building and where. We'll confirm which IP is available as PRO IP on your process, what is silicon-proven there, and how licensing works. If you don't see what you need, more IP is in active development.

Questions About Semiconductor IP

Semiconductor IP is a design block, already built and verified, that you license for your own chip instead of building it in-house. IP that goes into a silicon SoC is often called silicon IP. Typical examples are a MIPI PHY, an SRAM compiler, a standard cell library and an AMBA bus controller. Licensing proven IP frees your engineers for the logic that sets your product apart.

Foundation IP is the basic building blocks of a design: standard cell libraries, memory compilers and I/O. Interface IP connects the chip to sensors, displays, storage, other chips and in-vehicle networks, for example Mixel MIPI, LVDS and ASA PHYs, I3C, and automotive networking controllers such as CAN. System IP such as AMBA connects the blocks inside the chip.

PRO IP is available on TSMC, GlobalFoundries, Samsung, SMIC, STMicroelectronics, Tower and UMC processes, from 2 nm to 180 nm depending on the product line. The table above shows coverage for each line. Soft IP such as AMBA, I3C and automotive networking controllers is synthesized onto the node you choose. If you don't see your process, talk to the IP team.

Hard IP comes as fully characterized, DRC/LVS-clean instances with Liberty, LEF and GDSII views. Soft IP comes as synthesizable cores. Each family page lists its full deliverables. For example, Mixel IP also includes integration guidelines, models, test benches and support through production.

PRO IP is production-ready and available to license now, and much of it is silicon-proven. Mixel IP is silicon-proven on 13 nodes at 9 foundries, and Silvaco automotive networking controllers have shipped in more than one billion units. Ask the IP team about silicon status for a specific product and process.

PRO IP stands for Production-Ready Offerings: Silvaco hard IP characterized for specific foundry processes, and synthesizable soft IP, available to license now. Every PRO IP product is listed in the PRO IP Product Selection Guide.