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SmartSpice is Silvaco’s parallel SPICE simulator for transistor-level circuit design. Give it a SPICE netlist written for HSPICE or Spectre and it reads the file directly. Legacy PSPICE and Berkeley SPICE files work too. If a circuit won’t converge on one method, SmartSpice surveys the initial conditions and moves on to other solvers and stepping algorithms. Accuracy holds throughout.
SmartSpice picks its solvers, stepping algorithms and computation methods during the run, not up front. Capacity runs past 8 million active devices.
Run it multi-threaded on one machine or distributed across CPUs on your network. For large transient runs, HPP mode splits the circuit into partitions and solves them in parallel across cores, pre- or post-layout.
Set the target and let SmartSpice move the parameters. Performance measure optimization tunes trip point, delay, current limits, rise and fall times, or anything else a .MEASURE statement can calculate. Several targets can run at once.
Function curve optimization works on the whole curve: DC, AC or transient results fitted to a target from TCAD simulation or from measurement. Steady state, frequency domain or time domain, the analysis type doesn’t limit it. You watch the optimizer’s progress on an interactive display.
When the model you need doesn’t exist yet, write it. SmartSpice covers every analog feature in Verilog-AMS 2.3.1, and you debug the model inside the simulator. Small-signal and noise sources come in Gaussian, exponential, Poisson, chi-square, Student’s T and Erlang distributions. Its analog operators run from time integrals, derivatives and partial derivatives to transition, slew, Laplace and Z-transforms.
Prove a PLL, VCO or data converter architecture top-down with behavioral models, then verify each block bottom-up once the transistors exist. Digital blocks inside a mixed-signal design, a sigma-delta converter’s among them, get written the same way. Compile and encrypt the finished model, and it can go to a customer without its source.
Adjust a model or device instance parameter, or several together, and watch the circuit respond at once. It runs from SmartSpice or from the Gateway schematic.
Your first sizing pass becomes a conversation instead of a queue of reruns. Setups save, so the next block starts where this one left off. More on Circuit Rubberband
A SPICE netlist and a model set. The netlist comes from the Gateway schematic, an existing deck, or a post-layout extraction. Models come from your foundry’s PDK or from your own measured devices. Silvaco also supplies calibrated models for TFT, OTFT, SOI, HBT, FRAM and FinFET.
Waveforms, and a way back. SmartView opens the results for viewing, measurement and analysis. Gateway works the other direction: it drives rubberband tuning from the schematic, so a value you change there shows up in the result straight away.
Working in Cadence? SmartSpice runs inside the ADE environment in Spectre-compatible mode.
Six of the ten biggest semiconductor companies use Silvaco EDA. Here’s what SmartSpice work looks like up close, and none of it sits behind a form.
Mobile Semiconductor needed 56,000 SPICE runs to characterize its memory compiler across a 22nm node. After switching from a legacy simulator flow to SmartSpice and SmartView, the team reports a 50% gain in characterization time.
In Silvaco’s own tests, partition-based HPP mode ran up to 40x faster than standard SmartSpice, with maximum delay error near 2%. One simulation fell from roughly 90 hours to 2.2.
The datasheet: convergence and analysis options, the optimizer, HSPICE and Spectre compatibility, and every supported device model listed by family.
Analog designer Martin Mallinson, whose audio circuits have gone into millions of smartphones, on the interactivity, speed and precision he gets from SmartSpice.
Performance and memory, the new interface, SmartSpice RF, Pro and Server, Spectre compatibility mode, parallel .ALTER, and external sampling for Monte Carlo.
Target goals and parameter bounds, performance measure against function optimization, and when a local or a global method is the better call.
How to start the Verilog-A debugger inside SmartSpice and set breakpoints, conditional ones included.
TFT flat-panel circuit design in SmartSpice, recorded for on-demand viewing.
Send the deck that won’t converge, the corner run that takes too long, or the model you’d have to write in Verilog-A. An application engineer will run it in SmartSpice with you and tell you plainly where it fits.
It’s the parallel SPICE circuit simulator in Silvaco’s AI-Driven Design line, built for transistor-level analog and mixed-signal work, plus memory and custom digital. It loads HSPICE and Spectre decks, with their models, directly. Runs go multi-threaded on one machine or out across network CPUs, and a single circuit can exceed 8 million active devices.
SmartSpice is the general-purpose simulator, with DC, AC and transient analysis, built-in optimization, Verilog-A and rubberband tuning. SmartSpice Pro is Silvaco’s FastSPICE simulator for multi-million-element SRAM and TFT display circuits. It partitions the circuit, uses multi-rate event-driven simulation, and runs DC operating point and transient analyses only.
Foundry models in HSPICE or Spectre format, and SPICE netlist formats from HSPICE, Spectre, PSPICE and Berkeley SPICE. Built-in device models cover MOSFET, SOI, TFT, MESFET, JFET and diode families, with BSIM3, BSIM4, BSIM6, BSIM-CMG for FinFET, PSP and HiSIM among them. Anything missing can come in as Verilog-A.
Real-time circuit tuning. Move any mix of model and device instance parameters and the response redraws immediately, with no rerun to wait for. Start it from the SmartSpice interface or the Gateway schematic, then save the setup so the next circuit can pick it up.
Yes. Load a target curve from bench measurement or TCAD, and function curve optimization moves circuit and model parameters until the simulated DC, AC or transient response matches it. Working to a spec instead? Performance measure optimization targets values such as delay or current, more than one at a time.
Yes. SmartSpice implements the analog side of Verilog-AMS 2.3.1 in full. Its built-in debugger sets breakpoints in model source, conditional ones included, while the simulation runs. Compiled, encrypted models keep proprietary compact models and analog IP closed when you share them.