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Single and dual port SRAM compilers

Silvaco's SRAM compilers give SoC teams single- and dual-port embedded SRAM IP, configured per instance on named TSMC, GlobalFoundries and UMC processes, so the memory fits your chip instead of the other way round.

Talk to an IP specialist Request the SRAM compiler datasheet

SRAM compiler capabilities

Pick the variant that suits your power budget, then build the rest of the memory around it.

  • Optimization

    Choose a low-power, general-purpose or high-performance variant. Multiple power modes let you trade leakage against wake-up time, and several threshold-voltage (Vt) options and operating modes set how fast the array runs.

  • Architecture

    Low-power operation comes first in the design, with a high-density option for when area is the tighter limit. Nap, Retention and Nap plus Retention modes are there at 55 nm, 40 nm and below. Embedded power switches give you finer control, and you can run one supply or a separate rail for periphery and core.

  • Yield and integrity

    The compilers are verified against both global and local variation. Add ECC bits, and use flexible word size and addressing for redundancy. Where you need them, add a configurable write mask and built-in self test and repair (BIST/R).

  • Process coverage

    Twelve compilers carry part numbers in the current catalog, from 22 to 130 nm across TSMC, GlobalFoundries and UMC. The technology behind them spans 180, 152, 130, 110, 90, 85, 65, 55, 40, 28 and 22 nm, on G, LP and SOI CMOS and on high-voltage, BCD and eFlash offerings. If your process isn't among them, the compilers port.

  • Power and area

    The operating modes cut power consumption by up to 50%. Partitioned arrays stretch battery life, data retention mode lowers leakage current, and the high-density build saves area.

Low-power modes

Idle memory still leaks. These modes let you decide how much, against how long the next access can wait.

Mode Core Periphery What happens Wake-up Leakage vs Standby
ActiveOn at VddOn at VddReads and writes. Dynamic power plus a little leakage.——
StandbyOn at VddOn at VddPowered, not accessed. Leakage only, no dynamic power.Quick1.00×
NapOn at VddOffSource biasing on. An intermediate low-power state.One clock cycle, slightly slower than Standby0.69×
RetentionBelow VddOffCore held at the lowest voltage that keeps its data.Slow: periphery switches and circuits power up first0.54×
Retention + NapOn at VddOffSource biasing on, core at nominal voltage.Slow: periphery switches and circuits power up first0.28×
ShutdownOffOffEverything off. Data is lost.Slowest0.1×

Leakage is relative to Standby, as Silvaco publishes it for a 4Kx32 instance at the typical corner, 1.2 V and 25 °C. Nap, Retention and Retention + Nap are available at 55 nm, 40 nm and below. Which modes a given compiler carries is worth confirming with an IP specialist.

Where the SRAM compiler fits

  • Low-power SoC caches and buffersNap and Retention hold data while cutting leakage between accesses.
  • Battery-powered and IoT designsArray partitioning and a retention mode keep standby drain low.
  • High-performance compute blocksHigh-performance variants with several Vt options and operating modes.
  • Designs needing ECC and redundancyECC bits plus redundancy through flexible addressing, with BIST and repair if you want it.

Find your node, then the part number

Millions of wafers and thousands of designs already carry Silvaco's compiled memory. Start with your foundry and node. If a compiler exists there today, it has a part number.

SRAM compilers by foundry and node

Foundry Process Memory type Retention Size (bits) Mux Supply (V) Part number
GlobalFoundries22 nm FDX+Single-Port SRAMNo256–1,024k4, 8, 160.861251
TSMC40 nm uLPDual-Port SRAMYes64–288k40.9 / 1.161252
TSMC40 nm ULP eFlashDual-Port SRAMYes64–288k40.9 / 1.161253
TSMC40 nm LPSingle-Port SRAMNo256–576k41.161254
TSMC55 nm LP eFlashDual-Port SRAMNo256–32k81.261259
TSMC55 nm ULP eFlashDual-Port SRAMNo128–64k41.261260
TSMC55 nm HVSingle-Port SRAMNo512–320k8, 161.261261
GlobalFoundries55 nm LPxSingle-Port SRAMYes320k4, 8, 161.261263
TSMC90 nm LP eFlashDual-Port SRAMYes256–80k81.261264
UMC110 nm eFlashSingle-Port SRAMYes256–320k4, 8, 161.561266
TSMC130 nm BCDSingle-Port SRAMNo128–64k4, 8, 161.561267
TSMC130 nm BCD PlusSingle-Port SRAMNo128–64k4, 8, 161.561268

Size is the range of bits each compiler generates. Process not in the table? Ask an IP specialist about a port.

  • 22–130 nmpart-numbered compilers at TSMC, GlobalFoundries and UMC
  • 12 foundries and IDMswhere Silvaco memory compilers are deployed
  • 0.28×Standby leakage in Retention + Nap
  • 25+ yearsof compiled memory design
  • Liberty · LEF · GDSIIdelivered with every characterized, DRC/LVS-clean instance

Ask about your node

Tell an IP specialist your foundry, node and the SRAM you need: capacity, ports and power modes. You'll learn whether there's a compiler on it now, what porting one would take, and how licensing works.

Talk to an IP specialist Request the SRAM compiler datasheet

SRAM compiler questions

An SRAM compiler generates embedded SRAM instances to the capacity, mux and word width a design specifies, so nobody lays out each memory by hand. Silvaco's compilers deliver fully characterized, DRC/LVS-clean single- and dual-port instances for a named foundry process, with the power modes that process supports.

A single-port SRAM handles one read or one write per cycle. A dual-port SRAM has two independent ports, so two accesses can land in the same cycle, and it takes more area to do it. Silvaco's catalog lists seven single-port and five dual-port compilers, all five dual-port on TSMC processes.

Part-numbered compilers cover 22, 40, 55, 90, 110 and 130 nm: GlobalFoundries 22FDX+ and 55LPx, UMC 110 nm eFlash, and TSMC from 40 to 130 nm on low-power, eFlash, high-voltage and BCD processes. Silvaco's wider node list adds 180, 152, 85, 65 and 28 nm. And if yours isn't there, a port is worth asking about.

Both are low-power states for an idle SRAM. Nap switches off the periphery and turns on source biasing, waking in one clock cycle at 0.69× Standby leakage, while Retention drops the core to the lowest data-holding voltage for 0.54×. Combine the two and leakage falls to 0.28×, on nodes from 55 nm down.

Yes, as an option. Built-in self test and repair (BIST/R) raises reliability and yield, and it works alongside ECC bits and the redundancy that configurable word size and addresses give you. The compilers are also checked for variation tolerance, local as well as global.

Each compiled instance is fully characterized and DRC/LVS-clean, with the Liberty models, LEF abstract and GDSII layout your flow expects. Supply can be single or split between periphery and core, and a write mask is there when the design calls for one.

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