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Viso is Silvaco's parasitic analysis tool for RC networks. Give it a parasitic netlist and it shows you where the extracted resistance and capacitance are costing the design. Crosstalk, weak signals, unbalanced net symmetry, delay degradation, IR drop: each one traced to its cause. You get that answer from the netlist alone, with no simulation in the loop.
Start with one metric across every net. Then drill down, layer by layer, to the RC segment that's causing it.
Measure crosstalk, signal weakness, RC delay, net symmetry and IR drop, plus pin-to-pin and access resistance, voltage maps and complex impedance. Compare nets directly, differential and parallel pairs included.
Point and click for an equivalent resistance or RC delay on the spot. Sanity checks flag shortcuts and disconnected instances within seconds.
Test a fix on the parasitics first. Remove, add or re-value a resistor or via, or change a whole layer's resistivity, then rerun the analysis without touching the layout.
Viso marks the elements driving each result on the layout itself. Overlay GDSII or OpenAccess data on the parasitics, and merge multi-finger pins with initial conditions you choose.
Load the full power network, however large. Map resistance, delay and voltage drop across it for debug or what-if exploration. Skip the power simulation you'd otherwise wait on.
Parasitic netlists above 100 GB and very large power nets both load, and render in 2D and 3D.
Viso links to Cadence Virtuoso. Every analysis also runs from the command line. The checks you trust in the GUI become batch verification scripts on every project.
Reads: DSPF, SPEF and SPICE parasitic netlists, CalibreView parasitic netlists, OpenAccess extracted views.
Writes: ASCII CSV and TSV results, plus a results database you explore in the GUI.
Runs on: Red Hat Enterprise Linux 7.9 and 8.x, and SLES12 SP5, x86_64.
Viso checks parasitics at two points. Early extractions, while the layout is still short of LVS-clean. And the sign-off extraction, ahead of simulation.
A parasitic netlist, and nothing else. DSPF, SPEF, SPICE or CalibreView, or an OpenAccess extracted view, from Hipex or a third-party extractor.
Cadence Virtuoso: Viso builds its parasitics view from Virtuoso's OpenAccess data, linked to your layout or extracted view. Hide a layer in Viso and it hides in Virtuoso too.
Whichever tool acts on what you found.
The datasheet has the specs. The talks show the analyses running on real circuits.
Every analysis, input and output format, and supported platform, on two pages.
The top-down method from a whole-net metric to a single RC segment, plus what-if edits and the Virtuoso link.
Root-causing parasitic problems on a high-speed LVDS block, from first symptom to fix.
Timing estimates, crosstalk and net matching used to pinpoint trouble spots in high-speed circuits.
The Viso features added for debugging parasitic structures without long simulation runs, alongside Jivaro's reduction updates.
Parasitic reduction with Jivaro and analysis with Viso, in one session.
Manuals and release notes, in Support and Downloads.
Send a parasitic netlist from a block that isn't meeting its targets. An application engineer runs Viso on it with you and shows where the layout is causing the problem.
Parasitic analysis examines the resistance and capacitance a layout adds to a circuit and finds where they hurt performance: crosstalk between nets, weak signals, broken symmetry, extra delay and IR drop. Viso runs it directly on the extracted netlist and marks the elements responsible on the layout, so you know what to fix.
Yes. Viso needs only a parasitic netlist and computes resistance, RC delay, crosstalk, net matching and voltage drop straight from it, with sanity checks that finish in seconds. Screen a design and test what-if fixes ahead of any long post-layout run, even while the layout isn't LVS-clean yet.
Viso reads parasitic netlists in DSPF, SPEF, SPICE and CalibreView formats, plus OpenAccess extracted views. That covers the output of Silvaco's Hipex and of third-party extractors. Results come out as ASCII CSV or TSV files for your scripts, and as a database you can explore in the GUI.
Viso takes parasitic netlists of more than 100 GB, along with very large power nets, and draws the network in 2D and 3D. Its analyses run fast enough for designs considered too large to simulate, in batch from the command line or interactively in the GUI.
Yes. Viso reads Virtuoso's OpenAccess data to create its parasitics view, then keeps a direct link between your layout or extracted view and the matching Viso database. Virtuoso mirrors the layer navigation and visibility changes you make in Viso, so you explore the layout and its parasitics together.
An extraction tool such as Hipex calculates the parasitics from the layout and writes them to a netlist. Viso picks up that netlist and tells you what it means for the design: which nets are weak, coupled, unbalanced or slow, and where on the layout the cause is.