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Standard cell library IP: CORE, Power Management and ECO Kits

Each Silvaco standard cell library is characterized for one named foundry process. Then it's open to tuning, so your SoC team sets the power, speed and area trade-offs instead of inheriting ours.

Talk to an IP specialist Download the IP catalog (PDF)

What each library gives you to work with

Pick the kit, the thresholds and the cell height that suit the design. Then change what still doesn't fit.

  • Library types

    CORE libraries for the logic, a Power Management Kit (PMK) for power gating and multi-voltage design, and an ECO Kit on a fixed front-end pattern, for late layout changes with a minimal number of mask changes. Configurable architectures fit each library to its process. Not to be confused with Power Management IP, the LDO regulators and bandgap reference.

  • Vt options

    Up to four thresholds per library, from RVT, LVT, HVT and ELVT. Put low-Vt cells on the critical paths and high-Vt cells everywhere leakage costs you more than speed does.

  • Track heights

    7T, 8T, 10T or 12T, depending on the library. Short cells pack more logic into each square millimeter. Tall ones leave room for bigger transistors and stronger drive.

  • Foundry enablement

    Libraries for TSMC, GlobalFoundries and UMC processes from 28 to 180 nm, each with foundry-qualified views. Low-power, embedded-flash and Bi-CMOS processes are on the list. Working on something else? Ask about your process.

  • What changes on the chip

    The libraries are built to push frequency up and leakage down while holding yield. Dense layouts put more gross die on each wafer. Interconnect gets shorter too, so cost per function drops and power efficiency rises.

Find your library by foundry and node

Ten libraries, each characterized for a single foundry process.

Transistor Vts: RVT (regular), LVT (low), HVT (high), UHVT (ultra-high), ULVT (ultra-low), ELVT (extra-low).

Part number Foundry Node (nm) Process Voltage (V) Track height Kits Transistor Vts Gate length (nm)
70350GF28SLP0.98TCORE, PMK, ECORVT, LVT, HVT, ELVT30, 34, 38
70351TSMC40LP1.17TCORERVT, LVT, HVT35, 40
70353GF55LPx0.97TCORE, PMK, ECORVT, LVT, HVT60
70354GF55LPx3.310TCORERVT500
70355UMC55LPeFLASH0.97TCORERVT, LVT, HVT60
70356TSMC65LP1.212TCORERVT, LVT, HVT65
70357TSMC110LP1.27TCORE, PMK, ECORVT110
70359GF130LP1.27TCORERVT, LVT110
70360TSMC180LP1.87TCORE, PMK, ECORVT180
70361GF180Bi-CMOS3.37TCORERVT500

GF is GlobalFoundries. CORE is the base library, PMK the Power Management Kit, ECO the ECO Kit. Need other PVT corners? Custom characterization is available on request.

Where the libraries fit your design

  • Low-power SoCs for mobile, IoT and wearablesLow-leakage cells, fine-grained drive strengths and the PMK stretch the battery budget.
  • High-density digital blocksMulti-bit and multi-height cells cut pin count and fit more function into the same rows.
  • Designs needing power gating and multi-voltage domainsThe PMK supplies the power-gating cells, plus the level shifters that sit between domains.
  • Late-stage ECO changesThe ECO Kit's fixed front-end pattern keeps late fixes out of the base layers.

What you can verify before the first call

Match a library to your process and flow on your own, then talk to us.

  • 10libraries with published part numbers, 70350 to 70361
  • 3 foundriesTSMC, GlobalFoundries and UMC
  • 28–180 nmGlobalFoundries 28SLP at one end, TSMC 180LP and GlobalFoundries 180 Bi-CMOS at the other
  • Thousandsof cells and cell variants per library, with drive strengths in fine steps
  • Liberty, LEF, GDSIIthe views your flow reads, DRC/LVS-clean on delivery

Bring us your node and your PPA targets

Name the foundry and node, and what the design has to hit. An IP specialist will tell you which library fits and what it takes to tune one that nearly does. You'll also hear how licensing and evaluation work.

Talk to an IP specialist Download the IP catalog (PDF)

Standard cell library questions

It's the set of pre-designed logic cells, from simple gates to flip-flops and multiplexers, that synthesis and place-and-route tools assemble into a digital block. Each cell arrives characterized for timing and power on one process. Silvaco supplies CORE libraries with optional Power Management and ECO Kits, delivered as Liberty, LEF and GDSII views.

Vt is the threshold voltage at which a transistor turns on. Lower-Vt cells switch faster and leak more; higher-Vt cells leak less and switch slower. Mixing them lets you spend leakage only on the paths that need the speed. Silvaco libraries carry up to four Vt flavors, depending on the process.

Track height is a cell's height counted in routing tracks, the metal pitches that fit across it. Fewer tracks give you denser logic. More tracks leave room for larger transistors and stronger drive. Silvaco's libraries come in 7T, 8T, 10T and 12T, set library by library.

An ECO kit holds cells laid out on a fixed front-end-of-line pattern. A bug found after layout is fixed by reconnecting those cells. Only a few masks change, not the whole set. Four of the ten Silvaco libraries in the catalog include one.

Ten libraries cover GlobalFoundries 28SLP, 55LPx (0.9 V and 3.3 V), 130LP and 180 Bi-CMOS; TSMC 40LP, 65LP, 110LP and 180LP; and UMC 55LPeFLASH. That spans 28 to 180 nm. If your process isn't among them, an IP specialist can tell you whether a custom characterization makes sense.

Yes, two ways. Silvaco can configure the architecture and add custom PVT corners, low-voltage operation included, on request. Or your team tunes it directly. CellForge 2D adjusts transistor sizing, row height and DFM rules across a whole library. LibertyForge LC then recharacterizes the result into Liberty timing and power models.

More foundation IP