What does Silvaco offer for analog and custom IC design?

Schematic capture and layout, DRC, LVS and physical verification, full-chip parasitic extraction, parasitic reduction and comparison, netlist analysis, and variation and yield analysis. Nine capabilities in one family, built to work together but licensed separately, so you can adopt the one that solves your problem without replacing the flow around it.

Is Silvaco a realistic alternative to Cadence Virtuoso?

That is a fit question rather than a ranking, and it depends on your flow. Expert imports existing Virtuoso technology-file information, reads and writes OpenAccess, and links to Calibre RealTime, Calibre Interactive and Calibre RVE. It is built to sit inside an established flow rather than to replace one. Evaluate it on your own layers.

Can a small design team afford this toolset?

Licensing is per tool on one, two or three year terms rather than as a bundle, so a small team can start with the single tool that solves its problem. Licences float from a server across the network. Academic and research groups have a separate low-cost track. Ask for pricing.

Can I use Silvaco tools alongside Cadence or Synopsys tools in the same flow?

Yes, and most customers do. SmartSpice is HSPICE and Spectre compatible for netlists and models. Expert reads and writes GDSII, OASIS, LEF/DEF and OpenAccess. Jivaro Pro reads DSPF, SPEF, HSPICE, Spectre and Calibre View, and is independent of the extraction and simulation tools either side of it.

What semiconductor IP does Silvaco license?

Two groups. Mixel PHY IP covers silicon-proven MIPI interface blocks, including D-PHY, C-PHY and the combo configurations. Foundation and system IP covers standard cell libraries, embedded memory compilers for SRAM, ROM and register files, and automotive networking blocks. Individual blocks are listed on the Design IP page.

Which foundries and PDKs are supported?

Seventeen foundries appear in the published coverage set, weighted towards specialty and mature nodes. Coverage is not only PDKs: it also includes DRC and LVS rule decks, standard cell libraries and memory compilers. Check your foundry and node before committing to an evaluation.

How does the design portfolio connect to Silvaco manufacturing tools?

Through two objects rather than a platform. Utmost IV extracts SPICE models from characterization data, and Victory RCx extracts parasitics from a simulated three-dimensional structure. Both are standard formats, so they feed this side of the portfolio, or any other vendor's simulator you already run.

How do I evaluate the portfolio?

Not by downloading it, because there is no self-serve trial build. An evaluation runs under licence on your own hardware, against your own design data, with a named application engineer attached throughout. Evaluations are governed by the Silvaco Evaluation License Agreement and a mutual non-disclosure agreement, both published.

Electronic design automation software and silicon IP

AI-Driven Design is Silvaco's electronic design automation and licensed IP: circuit simulation, custom layout and verification, plus the interface and foundation blocks you'd rather license than draw.

Talk to our Technical Experts

Product families: 3; Circuit Simulation, Analog and Custom IC, Design IP
Tools: 15; Nine of them in Analog and Custom IC, plus licensed IP
Span: Schematic → post-layout; Capture through to simulation with the parasitics in it

Pick the family that fits the job

Simulating a circuit, drawing and checking it, and licensing proven silicon are different jobs. Each gets its own set of EDA tools.

Circuit Simulation

SPICE simulation, plus the power, EM/IR and thermal analysis that shows whether your supply network holds up under load.

Explore Circuit Simulation

Analog and Custom IC

Schematic to layout, with verification, extraction and variation analysis in between. A DRC error or parasitic problem shows up while you can still move a polygon.

Explore Analog and Custom IC

Design IP

Silicon you don't have to design yourself. Mixel MIPI PHYs proven at nine foundries, plus standard cells, memory compilers and system IP you can tune.

Explore Design IP

Fits the flow you already run

Nobody replaces a qualified flow to try one tool. What matters is which formats cross the boundary, and where this portfolio stops. Both are below.

Covers Schematic capture through layout, physical verification, extraction and post-layout simulation for analog, mixed-signal and custom IC.

Does not Do digital implementation. There is no synthesis and no place-and-route here — nothing in this portfolio takes RTL and produces a placed, routed block.
Covers DRC, LVS and physical verification, inside the layout editor.

Does not Ask you to abandon a sign-off deck you are already qualified on. Expert links to Calibre RealTime for sign-off quality DRC on demand, and is integrated with Calibre Interactive and Calibre RVE.
Covers The whole parasitic chain — extract with Hipex, reduce with Jivaro Pro, analyse with Viso, compare decks with PEX Certify.

Does not Require Silvaco extraction to do it. Jivaro Pro is independent of the tools either side of it and reads DSPF, SPEF, SPICE3, HSPICE, Spectre and Calibre View.
Covers SPICE simulation at production scale, with the Verilog-AMS 2.3.1 analog subset for behavioural models.

Does not Need your decks rewritten. SmartSpice is HSPICE and Spectre compatible, so an existing deck runs as it is.
Covers Licensed silicon — MIPI interface PHYs, standard cell libraries, memory compilers and system blocks.

Does not Originate the device models you simulate against. Those come from the foundry PDK, or from the manufacturing side via characterization and extraction.

What crosses the boundary

Silvaco design tools with the file formats and third-party interfaces each supports, as published on silvaco.com
Tool	Formats in and out	Third-party interfaces
GatewaySchematic	SPICE, CDL, NDL, Verilog IEEE 1364, OpenAccess, iPDK	EDIF 2 0 0 to third-party schematic tools; drives HSPICE® as well as SmartSpice
ExpertLayout	GDSII, LEF/DEF, DXF, OASIS, CIF, Applicon, OpenAccess	Calibre® RealTime, Calibre Interactive and Calibre RVE; imports existing Virtuoso technology-file information
SmartSpiceSimulation	HSPICE® and Spectre® netlists and models; Verilog-AMS 2.3.1 analog subset	Runs an existing HSPICE or Spectre deck without a rewrite
HipexExtraction	In: GDSII, cell netlists, rule-based technology files	Back-annotates the schematic netlist with the extracted parasitics
Jivaro ProReduction	DSPF, SPEF, SPICE3, HSPICE®, SPECTRE®, Calibre® View, OpenAccess	Independent of the extraction and simulation tools either side of it

HSPICE and Spectre are registered trademarks of Synopsys and Cadence Design Systems respectively; Calibre is a registered trademark of Siemens EDA. Named here to state compatibility, not affiliation beyond the published EDA partnerships.

Days back on post-layout simulation

Design teams at 6 of the 10 largest semiconductor companies use Silvaco EDA software. Two customers timed their post-layout runs before and after Jivaro Pro.

20+ days6 daysfull simulation of one block, post-layout

"…a full simulation on one of our blocks would run 20+ days. After using Jivaro Pro this runtime was reduced to 6 days while maintaining the designer's accuracy requirements."

Harry Chan, Founder and CEO, eTopus
See parasitic reduction in Analog and Custom IC
At least 5×shorter post-layout SPICE runtimes at 40nm and 55nm

"…Jivaro Pro is consistently reducing post-layout SPICE simulation run times while maintaining accuracy, with at least a 5X improvement observed at the 40nm and 55nm nodes."

Yasuyuki Hattori, Senior Manager of IC Engineering, Alps Alpine Co., Ltd
See parasitic reduction in Analog and Custom IC

Release and version index

Current versions across the design portfolio, from the 2025 baseline release.

Current release version by product across the AI-Driven Design portfolio
Family	Product	Current version	Release date
Circuit Simulation	SmartSpiceIncludes RF and Pro	5.9.2.R	Not published
	SmartViewWaveform viewer	3.2407.1.R	Not published
	SmartSpice RadHard · Circuit Rubberband	Part of the SmartSpice line	Not published
	InVar	Not in the baseline release	Not published
Analog and Custom IC	GatewaySchematic editor	4.2407.0.R	Not published
	ExpertLayout editor	5.2407.0.R	Not published
	SmartToolsDRC, LVS and RDE	1.2407.0.R	Not published
	HipexFull-chip parasitic extraction	4.2407.0.R	Not published
	VarManVariation and yield	2023.1.3.R	Not published
	JivaroParasitic reduction	2025.1.25.R	Not published
	VisoNetlist analysis	2025.2.10.R	Not published
	PEX Diff · PEX LinkExtraction comparison	2025.1.17.R	Not published
Design IP	Mixel PHY IP · Foundation and system IP	Not on a software release cadence	Per process and node

Silvaco does not support virtual machines as licence servers, and does not publish release dates. Versions are revised through the year.

Release notes Downloads Full release table, all 27 products

Where your device models come from

AI-Driven Manufacturing is Silvaco's process and device side: TCAD, Lithography, Plasma and Photonics, plus FTCO. Utmost IV turns device data into SPICE models, and Victory RCx pulls parasitics out of TCAD's simulated 3D structures. That hand-off matters most when your node is too new for a mature model library.

Explore AI-Driven Manufacturing

Test it on a block you already know

Send a netlist or layout whose behavior you've already measured. An application engineer runs it on the tools that match, and you check the result against numbers you trust.

Talk to our Technical Experts

Before you shortlist anything

Everything between the schematic and sign-off, licensed tool by tool. You capture in Gateway, lay out in Expert, and run DRC and LVS on the layout. Extraction, parasitic reduction, netlist analysis and variation tools follow, and each one fits into your existing electronic design automation flow.

It depends on how much of your current flow you want to keep. Expert imports your existing Virtuoso technology-file data, handles OpenAccess in both directions, and hands off to Calibre RealTime for sign-off DRC. The fair test is one of your own blocks, on your own layers.

Yes, because you license tools one at a time, with updates and support included. Time-based licenses run one, two or three years per tool and float from a server across your network. Pricing isn't published, so ask about the one tool your team needs first.

Yes, and Cadence, Siemens EDA and Synopsys are all Silvaco EDA partners. SmartSpice takes your HSPICE and Spectre decks as they are, and Expert moves layout as GDSII, OASIS, LEF/DEF or OpenAccess. Jivaro Pro reduces DSPF, SPEF and Calibre View parasitics from any extractor.

Two groups, one of them built by Mixel's MIPI team since 1998. Mixel PHY IP spans MIPI D-PHY, C-PHY, CSI-2 and DSI, silicon-proven on 13 nodes at 9 foundries. Foundation and system IP adds standard cells, SRAM, ROM and register-file compilers, and AMBA, I3C and automotive blocks.

Seven foundries partner with Silvaco: ams AG, GlobalFoundries, ON Semiconductor, TSMC, Tower Semiconductor, UMC and X-FAB. What's supported depends on the process node, and the published PDK table lists a sample of it. If your node isn't in it, ask before you plan an evaluation.

Through two kinds of file your circuit flow already reads. Utmost IV writes SPICE models that Eldo, HSPICE, LTspice, QSpice, SmartSpice and Spectre can read. Victory RCx supplies parasitics from a simulated 3D structure, so either one feeds the simulator you already run.

With your own design, not a download, because there's no self-serve trial. You run a licensed evaluation on your hardware and data, with an application engineer alongside. The Evaluation License Agreement and mutual non-disclosure agreement that govern it are published, so your legal team can read them first.