SURGE Virtual Event North America 2025

Dr. Guichard brings you up to date on the Victory simulation tools, makes the case for TCAD in bringing up new devices, and sets out the TCAD roadmap.

Ciena's analog designers work from supplied models, and as geometries shrink, those models drift from reality: quantum effects take hold that classical simulators miss. So the team began building its own. Victory Atomistic handled the first requirements, since it solves Poisson and Schrödinger self-consistently, and joint work with Silvaco extended it from there. Fabrication detail on Ciena's 5nm devices was limited, yet the simulated trends follow room-temperature lab data well, if not point for point. The next target is qubit work, using simulation in place of costly cryogenic measurements. The solver still needs work to converge reliably at the coldest temperatures and lowest bias.

Etch simulation for TCAD has a scale problem: what happens across the plasma chamber and what happens inside one high-aspect-ratio feature have to be solved together. Dr. Filipovic's group links the two with machine learning and with feature-scale models informed by the equipment. Its surrogate models, trained on runs of the Hybrid Plasma Equipment Model (HPEM) plus experimental data, predict fluxes quickly. That speed opens the way to a digital twin and, in time, real-time optimization. The goal for the fab: less trial and error, and a greener process.

Matching TCAD parameters to measured data has mostly meant an expert working by trial and error, and that pace doesn't fit a shrinking time-to-market. This session hands the job to machine learning, using two Victory tools in one flow. Victory DoE runs the design of experiments across your TCAD simulations and collects the outputs. Victory Analytics then fits the TCAD parameters to your experimental data. The worked case is an AlGaN/GaN HEMT.

Process and fab engineers normally tune a fabrication step with wafer-based Design of Experiments. When one parameter keeps missing its target, that loop can stretch across weeks or months. The alternative is a simplified but accurate machine learning model of the step, and that approach is already in production use. Silvaco's FTCO platform builds the model from your fab data and TCAD data, as a semiconductor digital twin. Worked examples show the FTCO flow end to end, so you can judge where it fits your team.

Three device technologies, Si, GaN and SiC, and three ways to model them for SPICE: compact models, macromodels and Verilog-A. The bulk of the talk is one worked case, a SiC DMOS. Its extraction starts from I-V and C-V curves and the bias-dependent capacitances. From there the model is tuned on dynamic characteristics, and dynamic temperature effects go in last.

Ben Louie reports on the Analog and Custom IC portfolio: which features and functions are new, and the plan for Silvaco's EDA tools after them.

Power device layouts often carry many curved shapes, and curved geometry is hard for DRC engines to check. Stefano Pettazzi draws such a layout in Expert, then runs SmartDRC on it at speed with its accuracy intact. He ends on the joint TCAD and EDA flow Silvaco offers for power devices, so one supplier covers both halves.

Where exactly is the parasitic problem in an advanced-node block? Simulation will tell you, eventually. Viso goes straight to the extracted RC network instead, with timing estimates, crosstalk and net-to-net matching, and points you to the nets that need attention. The demo uses high-speed circuits and skips the long simulation loops.

Foundry processes don't stand still at SilTerra, and each enhancement sends its IP libraries back through optimization and validation. Siti Mariyam explains how Silvaco tools fit that loop in SilTerra's library development, and the characterization time they save.

Run standard cells at low voltage on an advanced FinFET node and the key metrics move: area, timing, power, variability. Fernando Carrion works through why, then introduces Silvaco's low-voltage FinFET libraries. Inside: a Power Management Kit (PMK), high fan-in cells whose transistor stacks are kept short, and flip-flops in multi-bit and retention versions. With multi-threshold options, you pick the trade between speed and power.

Porting a standard cell library to a new advanced node is slow by hand. Felipe Bortolon demonstrates Cello FinFET reusing an existing library for that move, and producing GDSII straight from CDL.

Two bandgap voltage references, designed by Silvaco on TSMC's N3P process (3nm FinFET), at 0.45 V and 0.92 V. Across -45°C to 150°C, each holds within 1%. That is the whole point of a reference circuit: an output that shrugs off process, temperature, supply and load, over time.

A capless LDO designed in TSMC's N3P 3nm FinFET process. The key figures:

• Load current: up to 30 mA
• Input: 1.2 V ±10%
• Output: programmable, 0.45–0.9 V in 50 mV steps
• PSRR: >40 dB at 1 kHz, >29 dB at 10 MHz, across all PVT corners (-40°C to 125°C)
• Load transient: <18 mV undershoot or overshoot for a 1 A/ns step, across the same corners
• Area: <3,400 µm²

Classic CAN, from 1986, settles bus contention by non-destructive arbitration: the higher-priority frame wins, and a faulty node is cut off while everyone else keeps talking. By 2011, ECU data packages had outgrown it, and CAN FD lifted the limits to 8 Mbps, with payloads of 64 bytes. CAN XL, the third generation, reaches 20 Mbps and 2,048-byte payloads. It also bridges to 10BASE-T1 and other Ethernet standards, as vehicle networks take on software-defined designs.