SURGE Virtual Event North America 2022

Superconducting electronics (SCE) can speed up computation, and it suits data-flow designs and machine learning algorithms well. The hard part is logic design, because every superconducting circuit style imposes constraints of its own. Prof. De Micheli connects those styles and constraints to synthesis, as groundwork for building SCE tool flows in more than one way. He closes on recent results.

Machine learning runs on custom ASICs at every scale: a few milliwatts in a phone, a dozen watts in a car, many kilowatts to train a large model. Cerebras built the top of that range. Its Wafer Scale Engine, a single ASIC with 2.4 trillion transistors, drives an ML supercomputer. Dr. Groeneveld traces how the software takes a PyTorch model and places it on that chip. There's synthesis, placement and routing, as in any ASIC flow, except the target here is an entire wafer.

The state of Silvaco's Victory TCAD simulation products in October 2022. Dr. Guichard also explains what TCAD contributes while a new device is still in development, and which way TCAD development is headed.

SiC power MOSFETs go into energy storage, industrial motor drives, electric vehicles, power supplies and solar inverters. Each new generation has to waste less energy, and getting there depends on predictive TCAD. For 4H-SiC, the models still need work. Dr. Dixit starts with bulk mobility. The usual mobility models can't predict how bulk resistivity changes with temperature, because they leave out the impurity scattering that dominates at low temperature. The talk replaces them with one complete, calibrated bulk mobility model for 4H-SiC. It tracks measured data closely enough for device simulation in TCAD.

Vision systems in cars, industrial machinery and high-speed communications links all depend on a photodiode turning light into a usable electrical signal. Detectors vary in topology and material, and TCAD applies across many of them, which opens it to many end markets. The worked case is an InGaAs avalanche photodiode. Sungwon Kong simulates and analyzes it, then extracts its key figures of merit. You see how TCAD lifts detector performance while cutting engineering, manufacturing and test cycles.

Some processes are driven by one uncharged particle: low-bias SF6 etching, for instance, or thermal atomic layer deposition and etch. Even these need careful physics before their topography can be predicted. Particle fluxes and surface kinetics together decide the result. Luiz Felipe Aguinsky surveys phenomenological process TCAD models that track a single particle, and shows how much the choice of flux model changes the simulated profile. He covers the flux models already in Victory Process alongside advanced ones from the Christian Doppler Laboratory. For low-bias SF6 etching, a Monte Carlo method is being prototyped inside Victory Process. For thermal atomic layer processing, a one-dimensional Knudsen-Langmuir model is built entirely in the Open Model Library, proof that you can extend Silvaco TCAD with models of your own.

Two needs brought Ciena to atomistic simulation. The supplied models behind its analog design lose accuracy as devices scale, because classical tools can't see the quantum effects that take over. And its qubit research needs device behavior at cryogenic temperatures, which the team could measure, but only at high cost and with a complex process. Quantum device modeling calls for a tool that solves the Poisson and Schrödinger equations together, self-consistently. Victory Atomistic (ViA) met that bar, and close work between the Silvaco and Ciena teams filled in the details. ViA now reproduces Ciena's lab results for its in-house 5nm devices at room temperature. For the qubit research, the aim is to replace cryogenic measurement with simulation. Future work improves ViA on several fronts, starting with convergence deep in the cryogenic range.

Better copper interconnects in the BEOL, from two selective techniques. A SAM deposits only on chosen materials, and ELD grows metal only where it's wanted. Combined, they improve device properties. Tokyo Electron's experiments and the Silvaco simulations show the same trend, which makes the case for the process.

A useful prediction for a nanodevice needs atomistic resolution, a consistent account of every quantum effect, and realistic incoherent scattering off phonons and impurities. Atomistic quantum transport is widely assumed to cost too much compute or to leave scattering out. Victory Atomistic handles all three, and Prof. Kubis presents its new modeling features for 2D materials and carbon nanotubes. Some atomistic runs still need a few CPU hours, so Silvaco and Purdue are connecting atomistic simulation to TCAD. The aim is answers you can rely on, in the run times TCAD users expect.

Building a complex device structure in process simulation often comes with a hard requirement: match the etch profile the fab actually produced, as seen under the transmission electron microscope. Victory Process has several geometric etch models that get there efficiently. Alexander Toifl puts them to work on FinFET and memory structures, shaping fins, reproducing non-ideal profiles with bowing and twisting, and running self-aligned multi-patterning.

Thomas Blaesi covers what's new in Silvaco's analog custom design tools, then sets out the EDA roadmap.

The 2022 Baseline release of Utmost IV added the Corner and Retargeting Module to Silvaco's device modeling platform. Bogdan Tudor shows it, then turns to recent models and technologies where Utmost IV played a part. He finishes with Silvaco's SPICE modeling services, for teams that would rather hand the modeling work over.

Silicon Creations sells IP across a wide spread of processes, and this is its flow through Silvaco tools. On the front end, Gateway handles porting between 12 foundries, at nodes from 180nm down to 3nm. Expert covers the back end. Simulation runs in SmartSpice, Silos and Variation Manager. Chung-Chun Chen takes each stage's challenges in turn, and shows the flow keeping IP development efficient from 3nm to 350nm.

Two problems in flat panel display design: TFTs with four terminals, and image retention. A good share of today's TFT technologies use a fourth terminal, and Silvaco's four-terminal TFT compact model is built for them. Dr. Matos describes how the model behaves and the extra room it gives modeling and design teams. Image retention has troubled displays for years. To fix it, or even limit it, display makers and consumer electronics companies have to simulate it at the SPICE level. SmartSpice Flex Modeling handles that simulation, along with other dynamic device effects.

VarMan has been deployed worldwide for years, and customer feedback from all that use shaped this release. It brings a redesigned GUI and improved algorithms, and keeps the accuracy and flexibility VarMan is used for. The aim is variation analysis that a wider group of your engineers can pick up.

Post-layout parasitics slow SPICE simulation, and advanced process nodes slow it most. Jivaro's new Pro module reduces the parasitic network so those simulations run much faster. Viso works the other side of the problem. Its new features let you understand and debug parasitic structures directly, before you commit to a long simulation.

Ben Louie reviews Silvaco's Design IP portfolio and the direction Silvaco is taking it.

Debug, trace and failure analysis over an I3C bus, with no extra pins. The Simplified Address-Mapped (SAM) debug add-on for I3C carries data from the application to the peripheral under debug, and back, on the bus's existing SCL and SDA lines. Ashish Senapati details the add-on IP and how it connects to common debug and trace adapters: ARM DAP, ARM-ETM/SWO, JTAG-TAP and RISC-V DMI/DM.

Every microcontroller reaches end-of-life. If your product carries years of software written for one MCU, moving it to another part is rarely simple. One answer is to build a functional replacement of your own, and Errett Hogrefe covers the design considerations and implementation choices along that path. Each replacement is a custom project that draws on a range of IP, and Silvaco supplies both IP products and design services for it.

SilTerra keeps developing and enhancing its processes, so its standard cell and I/O libraries must be re-optimized and re-validated to match. For a small team, that load adds up. Faris Amsyar walks through where that work gets difficult and shows Cello, Viola and SmartSpice each taking a share of it, so library development and validation finish sooner.

FinFETs gave chip designs more density and performance at lower power than planar layouts did. They also made standard cell design rules far harder. A violation often can't be fixed where it sits: it spreads across a large part of the cell and involves many layers. That slows the first layout, every migration to a new node and any specialization of the library. Dan Fitzpatrick picks out the hardest parts of FinFET standard cell layout and shows how Cello FinFET handles them.