SURGE Virtual Event North America 2023

Getting from a functional description to a mask pattern takes a long chain of algorithms. Some are numerical solvers. Others are heuristics kept because they work. Each one carries parameters tuned by hand, like the relative costs that trade area against speed. Some recent tools let machine learning find a design-specific parameter set, by running the flow over and over and reading the gradients out of the PPA results. Research now aims at tools that are ML-driven at the core, in placement and in routing. Dr. Groeneveld maps where ML in EDA stands and what it could change over the next ten years.

TCAD models how a device is made and how it runs, and it has become essential to deploying new semiconductor technology. Its models have become accurate enough to serve as digital twins of the manufacturing process itself. That opens two uses. Before production, you develop the technology virtually, run fewer physical experiments and reach yield sooner. During production, the same twin tunes fab processes, tracks variation and flags malfunctions. Dr. Camposano shows TCAD examples that work this way.

A status report on Silvaco's Victory TCAD simulators from the executive who runs TCAD. It covers the products themselves, the part TCAD plays whenever a new device family is developed, and where TCAD development is heading.

Switching can push a power device into abnormal overload, and some applications specify how much abuse the device must survive, through short-circuit and UIS tests. Mixed-mode circuit simulation reproduces these events. Tune its parameters against experiment and it predicts electrothermal behavior through the dynamic phase. STMicroelectronics used Silvaco TCAD to test what one defect in the active area does under short circuit. The defect dot sat in three places: the flat body/drain interface, the SiC/oxide interface along the channel, and the curved body/drain interface. A sensitivity study on its position rounds out the work.

How much of the magnesium in a p-GaN gate actually activates shapes the off-state of a normally-off p-GaN/AlGaN/GaN HEMT. The study starts in TCAD, comparing Mg doping profiles through their band diagrams. Capacitance–voltage measurements then reveal the p-GaN's net acceptor concentration. Devices with a magnesium-free GaN gate are set against devices activated by a reference anneal, and against a third group with improved activation. That last group gains on several parameters, in the off-state and the on-state alike.

After two decades of research, lateral GaN power devices are close to commercial maturity for switching up to the 650 V class. They still fall short of the material's theoretical limit on RDS_ON × A against breakdown voltage. Blocking strength trades against dispersion, and GaN on silicon caps vertical blocking. FBH is working two ways around that. Vertical GaN transistors take less wafer area than lateral HFETs, which cuts RDS_ON × A by an order of magnitude. Strain-free homoepitaxy also allows thick, lightly doped drift layers that block more than 1 kV. Lateral HFETs on an AlN buffer confine the channel behind a large conduction band offset, for stronger blocking and less dispersion.

FBH's labs use Silvaco simulation to design these devices, predict their behavior and make sense of the measurements. The talk compares simulated conductance of GaN fin MISFETs with experiment as geometry and epitaxial layers change. It shows edge terminations for vertical devices engineered with avalanche models, and traces the dynamic on-resistance of AlN/GaN HFETs to trapping and de-trapping.

Why Kepler Computing exists, and what it's doing to take memory design beyond CMOS. Debo Olaosebikan also shows how his team simulates those new memories in Silvaco TCAD.

Advanced CMOS and RRAM both need electron transport simulated accurately at the nanoscale. François Triozon reviews how far quantum transport simulation has come lately, and what it adds to device optimization. With 3D simulation in the NEGF (Non-Equilibrium Green's Functions) formalism, you can pin down access resistance in tri-gate CMOS devices. The same approach now estimates contact resistance where the channel is a 2D material. RRAM is harder. For OxRAM and tunnel junctions, linking ab initio simulation to quantum transport still leaves gaps in the picture of how the device operates.

MRAM is fast, durable and nonvolatile, which makes it a strong candidate to replace charge-based memory. Several designs switch its logical state with spin-polarized currents. Engineering problems still hold back wider adoption, and solving them takes simulation flexible enough to model how an MRAM cell really operates. Nils Jørstad presents recent results from a finite element approach that simulates charge, spin and magnetization dynamics together.

Quantum transport modelers have argued over theory and prototype code for 30 years. The early test devices, 2D electron gases and room-temperature resonant tunneling diodes, date from the 1980s and 1990s, and today's transistors have shrunk to those same critical sizes. Industry now needs predictive, quantitative models for devices near the few-nanometer limit. Gerhard Klimeck explains why it settled on the Non-Equilibrium Green Function method with an atomistic tight-binding basis. His group's NEMO5 implementation runs at Intel, and Silvaco sells a commercial version. Through nanoHUB and chipshub, NEMO versions reach students and researchers as simple apps for exploring concepts and running detailed analysis.

Could transistors with 2D channels take over from silicon? Once a FET channel is only a few atomic layers thick, only an atomistic model can answer that. Dr. Blaise shows Victory Atomistic applying quantum mechanics to the question, as support for prototyping a 2D transistor inside a professional TCAD environment.

Dan Fitzpatrick lists the new features and functions in Silvaco's analog custom design portfolio, then turns to the plans for Silvaco's EDA solutions.

Si, GaN and SiC power devices each bring their own particularities to SPICE modeling. Bogdan Tudor weighs compact models against macromodels as ways to capture them. Power FETs take the longest stretch, on two problems: bias-dependent capacitances, and tuning the model to dynamic characteristics. He closes with what Silvaco's modeling team has learned about parasitic elements and model accuracy in power devices.

Silvaco is Tower Semiconductor's main standard cell library provider, across all of Tower's technologies. The newest libraries serve a 65nm advanced power management process, with advanced characterization and MTBF calculation included. On the analog side, Tower supports and qualifies its iPDK and SPICE models in Silvaco's design flow, using Expert, Gateway, SmartLVS and SmartDRC.

Efficiency comes first, whether the target is a battery-powered device or an AI/ML accelerator in the cloud. Running logic and SRAM at one shared voltage, with dynamic voltage and frequency scaling, gets the most from both. The SRAM macros often set the limit, on voltage range, speed and reliability. Aril's SRAM, optimized on an advanced CMOS process, targets fast, reliable operation from 0.45 V to 0.8 V and above. Pair it with an efficient microarchitecture and tuned physical design, and the aim is the most performance per watt, whether the engine runs compute, graphics or AI/ML work.

At 4 K (−269°C), transistors stop behaving the way they do across the usual −55°C to 125°C range, so models built for that range don't apply. Silvaco's Analog and Interface IP team still delivered a fully functional 2 Gbps LVDS I/O for that temperature. Silvaco's modeling team built model files at 4 K. The IP team then designed and laid out the PHY and produced its collateral and views, all in Silvaco EDA tools. The PHY:

• A transmitter, a receiver and an accessory block
• 3.5 mA transmitter drive into a 100 Ω load, independent of PVT
• 100 Ω termination between the receiver's PAD+ and PAD− terminals, also independent of PVT
• Programmable equalization for board, signal-integrity (SI) and power-integrity (PI) compliance

Viso is built around the parasitics alone. Working on the extracted RC network itself, it analyzes interconnect quickly and points to the problem areas, which matters because those networks can decide how a circuit behaves. It also estimates timing and compares extracted netlists accurately. The demonstration uses a real-world circuit design.