SURGE Virtual Event EMEA 2023

Getting from a functional description to a mask pattern takes a long chain of algorithms. Some are numerical solvers. Others are heuristics, kept because they work. Every one has parameters engineers tune by hand, such as the relative costs that trade area against speed. A few recent tools hand that tuning to machine learning. They run the flow many times over and read the gradients out of the PPA data, converging on a parameter set for the one design. Research goes further, toward EDA tools that are ML-driven throughout, some for placement and others for routing. Dr. Groeneveld sets out where ML in the EDA flow stands now, and what it's likely to change over the next ten years.

TCAD already models how a device is made and how it then behaves, and new semiconductor technology rarely reaches production without it. Its accuracy now supports a bigger role: a digital twin of the manufacturing process, used to simulate that process and optimize it. Before production, the twin lets you develop a technology virtually, with fewer physical experiments and a shorter road to yield. Inside the fab, it can refine the process, watch for variation and catch malfunctions. Dr. Camposano explains the idea, with examples of TCAD models doing that job.

What's new across Silvaco's Victory TCAD tools, and the part TCAD plays when a new device is developed. Dr. Guichard ends on the plans for TCAD development.

A switching power device can be pushed into overload. Some applications write robustness limits into the spec and prove them with short-circuit and UIS tests. Mixed-mode circuit simulation reproduces those events, and once its parameters are tuned against experiment, it predicts the electrothermal behavior through the dynamic phase. This study uses Silvaco TCAD to put a single defect dot in a SiC device's active area. Then it watches the short circuit play out. The dot sits in three places in turn: the flat body/drain interface, the SiC/oxide interface along the channel and the curved body/drain interface. A sensitivity check on position follows.

How much of the magnesium in a p-GaN gate is electrically active shapes the off-state of a p-GaN/AlGaN/GaN HEMT. The work starts in TCAD, running several Mg doping profiles and reading the band diagrams they produce. Capacitance–voltage measurements then pin down the p-GaN's net acceptor concentration. On the bench, devices with a magnesium-free GaN gate go up against devices activated with the reference anneal. A device with improved activation comes out ahead on several off-state and on-state parameters. For normally-off GaN HEMTs, activation is the step to get right.

Lateral GaN power devices are close to commercial maturity for switching up to the 650 V class. They still fall short of the material's theoretical limit for RDS_ON × A against breakdown voltage. Part of that gap is a trade-off between blocking strength and dispersion; part is the limited vertical blocking of GaN on silicon. Two device routes aim to close it:

• Vertical GaN transistors take less wafer area than lateral HFETs, which brings RDS_ON × A down tenfold, to 1.0 mΩ·cm². Strain-free homoepitaxy also allows thick drift layers with low background doping, for blocking above 1 kV.
• Lateral HFETs on an unintentionally doped AlN buffer confine the GaN channel with the large conduction band offset at the buffer interface. The result is stronger blocking and less dispersion.

FBH develops both with physics-based simulation, and Dr. Bahat-Treidel shows where Silvaco tools do the work:

• FBH simulates the conductance of GaN fin MISFETs, checks it against measurement and predicts how it shifts with geometry and epitaxial layers.
• For vertical devices, avalanche models shape the edge terminations, and the results go up against experiment and theory.
• In the AlN/GaN lateral HFET, simulated trapping and de-trapping, with an avalanche model fitted to the epitaxial stack, explains its unusual dynamic on-resistance.

Debo Olaosebikan introduces Kepler Computing: why it was founded, and how it's making design beyond CMOS practical, with memory at the front of the queue. Silvaco TCAD is how Kepler simulates those new memories.

Advanced CMOS devices and RRAM both need electron transport at the nanoscale simulated accurately. François Triozon reviews what quantum transport simulation has achieved lately, and what it now brings to device optimization. In tri-gate CMOS, three-dimensional simulation using the Non-Equilibrium Green's Functions (NEGF) formalism puts an accurate number on access resistance. The same methods now evaluate contact resistance in transistors whose channel is a 2D material. RRAM, in its OxRAM and tunnel-junction forms, is harder: coupling ab initio simulation with quantum transport still leaves parts of device operation unexplained.

MRAM is fast, durable and nonvolatile, which makes it a serious candidate to replace charge-based memory. Several designs switch its logical state with spin-polarized currents. Engineering problems still hold back wide adoption, so there's real demand for simulation software flexible enough to model an MRAM cell in operation. Nils Jørstad presents the latest results from a finite element approach that simulates the cell's charge, spin and magnetization dynamics.

Quantum transport modelers have argued over theoretical approaches and prototype codes for 30 years. The test devices of the 1980s and 1990s were 2D electron gases and room-temperature resonant tunneling diodes. Today's transistors have reached the size and behavior of those early structures. So industry now needs device models that predict quantitatively, right down to the last few nanometers of scaling. Gerhard Klimeck explains why it chose NEGF with an atomistic tight-binding basis, and how his group's NEMO5 became the implementation the community adopted. Intel uses it today and Silvaco has commercialized it. Versions of NEMO also run as simple apps on nanoHUB and chipshub. Students and researchers use them to explore the concepts and run detailed analysis.

Could a transistor with a 2D channel replace silicon? Once the channel is only a few atomic layers thick, atomistic simulation looks like the only way to answer that. Dr. Blaise puts the question to Victory Atomistic, which answers it from quantum mechanics. He shows how the tool supports prototyping a 2D transistor inside a professional TCAD environment.

Dan Fitzpatrick, who runs Silvaco's EDA business, takes you through the new features in its analog and custom design tools. Then he looks ahead to the EDA products still to come.

Silicon, GaN and SiC each bring their own strengths and quirks to a power device, and a SPICE model has to respect them. Bogdan Tudor compares how compact models and macromodels handle the job. Most of the session goes to power FETs: how to handle their bias-dependent capacitances, and how to tune the model against dynamic behavior. He closes on the problems particular to power devices, parasitic elements and model accuracy among them.

Silvaco is Tower Semiconductor's main standard cell library supplier, across all of Tower's technologies. The newest set targets Tower's 65nm advanced power management process, with in-depth characterization and MTBF performance calculated. The work runs the other way too. Tower supports and qualifies its iPDK and SPICE models on Silvaco's analog design flow, from Expert and Gateway to SmartDRC and SmartLVS.

Battery-powered devices and cloud AI/ML accelerators want the same thing: more work per watt. Running logic and SRAM on one supply, and scaling voltage and frequency together, gets the most from both. The catch is the SRAM macros: their voltage range, speed and reliability set the limit. The SRAM technology Sinan Doluca presents is built on an advanced CMOS process. It targets fast, reliable operation from 0.45 V to 0.8 V and above. Pair it with a lean microarchitecture and careful physical design, and it pushes performance per watt up in compute, graphics and AI/ML engines.

Silvaco's analog and interface IP team designed and delivered a fully functional 2 Gbps LVDS I/O that runs at 4 K, or −269°C. At that temperature, devices stop following the characteristics engineers know from the standard −55°C to 125°C range. So the modeling team first built model files for 4 K. The IP team then designed and laid out the I/O and produced its collateral and views, all with Silvaco EDA tools.

The LVDS PHY combines a transmitter, a receiver and an accessory block, with PVT-independent performance. The transmitter drives 3.5 mA into a 100 Ω load and carries programmable equalization for board, signal integrity and power integrity compliance. The receiver has a PVT-independent 100 Ω termination between its PAD+ and PAD− terminals.

Parasitic RC networks can change how a circuit behaves, and Viso analyzes their electrical properties quickly. It works on the interconnect itself, so it narrows a problem down to the nets responsible. Its interface marks the troublesome parasitics, estimates timing and compares extracted netlists accurately. The demo runs on a real-world circuit design.